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ADS1283IRHFR

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Texas Instruments Analog To Digital Converters (ADC), VQFN-24-EP(4x5). Datasheet-verified pinout, KiCad symbol/footprint/3D.

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Contents

README

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ADS1283IRHFR

Texas Instruments · Analog To Digital Converters (ADC) · VQFN-24-EP(4x5)

ADS1283IRHFR from Texas Instruments, in a VQFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRDY output Data ready output, active low, pulses to indicate new conversion data available.
2 DOUT tri_state Serial interface data output, tri-state output high impedance when CS is high.
3 DIN input Serial interface data input, data clocked in on rising edge of SCLK.
4 CS input Serial interface chip select, active low, enables ADC serial interface when low.
5 SYNC input Synchronize input, rising edge active, resets digital filter and modulator.
6 MFLAG output Modulator overrange flag output, high when differential input exceeds ±100% full-scale.
7 DGND power_in Digital ground, tie to digital ground plane for low impedance reference.
8 CAPN output PGA output negative node, connect 10-nF C0G capacitor from CAPP to CAPN for anti-alias filtering.
9 CAPP output PGA output positive node, connect 10-nF C0G capacitor from CAPP to CAPN for anti-alias filtering.
10 AINP2 input Positive analog input 2, input range AVSS + 0.7 V to AVDD - 1.25 V.
11 AINN2 input Negative analog input 2, input range AVSS + 0.7 V to AVDD - 1.25 V.
12 AINP1 input Positive analog input 1, input range AVSS + 0.7 V to AVDD - 1.25 V.
13 AINN1 input Negative analog input 1, input range AVSS + 0.7 V to AVDD - 1.25 V.
14 AVDD power_in Positive analog power supply, 4.75 V to 5.25 V above AVSS for unipolar or ±2.5 V operation.
15 AVSS power_in Negative analog power supply, -2.6 V to 0 V relative to DGND.
16 VREFN input Negative reference voltage input, range AVSS - 0.1 V to VREFP - 1 V, typical 1 V to 5 V.
17 VREFP input Positive reference voltage input, range VREFN + 1 V to AVDD + 0.1 V.
18 PWDN input Power-down input, active low, disables internal circuitry to minimize power dissipation.
19 RESET input Reset input, active low, resets registers to default and restarts conversion process.
20 DVDD power_in Digital power supply, 1.65 V to 3.6 V, separate from analog supplies.
21 DGND power_in Digital ground, tie to digital ground plane for low impedance reference.
22 BYPAS output 1.8-V sub-regulator output, connect 1-μF ceramic capacitor to DGND for noise reduction.
23 CLK input Master clock input, nominal 4.096 MHz, requires low-jitter crystal oscillator source.
24 SCLK input Serial interface shift clock input, clocks data into DIN and out of DOUT on rising and falling edges.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24-EP(4x5)
Category Data Acquisition
Pins 25

CAD (KiCad official)

  • Symbol: ADS1283IRHFR
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: VQFN-24-EP(4x5) (KiCad packages3D, STEP)
  • 3D model files: ads1283irhfr-etched.step / ads1283irhfr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1283irhfr.step / ads1283irhfr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (68 pp, sha256 a109452d7280f730, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF