component
ADS127L01IPBS
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADC), TQFP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADS127L01IPBS
Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(5x5)
ADS127L01IPBS from Texas Instruments, in a TQFP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LVDD | power_out | 1.8-V analog supply from internal LDO regulator (INTLDO=0) or input (INTLDO=1); decouple with 1-µF capacitor to AGND. |
| 2 | CAP1 | output | Modulator common-mode voltage output; connect a 1-µF capacitor to AGND. |
| 3 | AINN | input | Negative differential analog input for ADC measurement (range AGND-0.3V to AVDD+0.3V). |
| 4 | AINP | input | Positive differential analog input for ADC measurement (range AGND-0.3V to AVDD+0.3V). |
| 5 | AGND | power_in | Analog ground reference. |
| 6 | AVDD | power_in | Analog-supply voltage input (2.7V to 3.6V); connect a 1-µF capacitor to AGND. |
| 7 | REXT | input | Analog power-scaling bias resistor pin; connect 60.4-kΩ resistor (HR/LP modes) or 120-kΩ (VLP mode) to AGND. |
| 8 | INTLDO | input | LVDD voltage selection pin; pull high to AVDD (external 1.8-V supply) or low to AGND (internal LDO) through 10-kΩ resistor. |
| 9 | REFP | input | Positive analog reference input; connect minimum 10-µF capacitor between REFP and REFN. |
| 10 | REFN | input | Negative analog reference input. |
| 11 | CAP2 | output | Reference common-mode voltage output; connect a 1-µF capacitor to AGND. |
| 12 | FILTER1 | input | Digital filter select pin bit 1; pull high to DVDD or low to DGND through 100-kΩ resistor. |
| 13 | FILTER0 | input | Digital filter select pin bit 0; pull high/low through 100-kΩ resistor; 00=WB1, 01=WB2, 10=LL, 11=Reserved. |
| 14 | FSMODE | input | Frame-sync mode select pin; pull high (master mode) or low (slave mode) through 100-kΩ resistor; applies to Frame-Sync interface only. |
| 15 | OSR1 | input | Oversampling ratio select pin bit 1 for decimation filters; pull high/low through 100-kΩ resistor. |
| 16 | OSR0 | input | Oversampling ratio select pin bit 0; pull high/low through 100-kΩ resistor; wideband filters 00=32x, 01=64x, 10=128x, 11=256x. |
| 17 | START | input | Synchronization signal (active high) to start or restart ADC conversion. |
| 18 | DAISYIN | input | Daisy-chain input for cascaded device configurations; tie directly to DGND if not daisy-chaining. |
| 19 | DRDY/FSYNC | bidirectional | SPI interface: data ready output (active low); Frame-sync interface: frame-sync input signal for synchronization. |
| 20 | DOUT | output | Serial data output from ADC (24-bit or 32-bit format); high-impedance when CS=1 in cascaded SPI configurations. |
| 21 | DIN | input | Serial data input for SPI interface; tie directly to DGND when using frame-sync interface mode. |
| 22 | SCLK | bidirectional | Serial clock input for SPI interface (0 to DVDD+0.3V); functions as input/output depending on interface configuration. |
| 23 | CS | input | Chip select input (active high in SPI cascaded configurations); tie directly to DGND when using frame-sync interface; controls DOUT tri-state. |
| 24 | CLK | input | Master clock input for internal timing and ADC modulator operation. |
| 25 | CAP3 | output | Internally-generated digital operating voltage output; connect a 1-µF capacitor to DGND. |
| 26 | DGND | power_in | Digital ground reference. |
| 27 | DVDD | power_in | Digital-supply voltage input (1.7V to 3.6V); connect a 1-µF capacitor to DGND. |
| 28 | RESET/PWDN | input | Reset or power-down pin (active low); asynchronous reset of all registers when pulled low. |
| 29 | HR | input | ADC operating mode select; pull high to DVDD (high-resolution mode) or low to DGND (LP/VLP mode) through 100-kΩ resistor. |
| 30 | FORMAT | input | Interface protocol select; pull high to DVDD (Frame-Sync mode) or low to DGND (SPI mode) through 100-kΩ resistor. |
| 31 | AGND | power_in | Analog ground reference. |
| 32 | AVDD | power_in | Analog-supply voltage input (2.7V to 3.6V); connect a 1-µF capacitor to AGND. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TQFP-32(5x5) |
| Category | Data Acquisition |
| Pins | 32 |
CAD (KiCad official)
- Symbol:
ADS127L01IPBS - Footprint:
Package_QFP:TQFP-32_5x5mm_P0.5mm - 3D model: TQFP-32(5x5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.1 mm nominal TQFP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
ads127l01ipbs-etched.step/ads127l01ipbs-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads127l01ipbs.step/ads127l01ipbs.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (90 pp, sha256
7af2117fe188e693, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).