component
ADS125H02IRHBT
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADCs), VQFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADS125H02IRHBT
Texas Instruments · Analog To Digital Converters (ADCs) · VQFN-32-EP(5x5)
ADS125H02IRHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REFP0 | input | Reference input 0 positive. |
| 2 | CAPP | output | PGA output P; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN. |
| 3 | CAPN | output | PGA output N; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN. |
| 4 | AVDD | power_in | Low-voltage analog power supply (5 V); recommended range is 4.75 V to 5.25 V. |
| 5 | AGND | power_in | Analog ground; connect to the ADC ground plane. |
| 6 | REFOUT | output | 2.5-V reference output; connect a 10-µF capacitor to AGND. |
| 7 | RESET | input | Reset; active low. |
| 8 | START | input | Conversion start, active high. |
| 9 | CS2 | input | Serial interface chip select 2 to select the PGA for communication. |
| 10 | CS1 | input | Serial interface chip select 1 to select the ADC for communication. |
| 11 | SCLK | input | Serial interface shift clock. |
| 12 | DIN | input | Serial interface data input. |
| 13 | DRDY | output | Data-ready indicator; active low. |
| 14 | DOUT/DRDY | output | Serial interface data output and data-ready indicator (active low). |
| 15 | BYPASS | output | 2-V subregulator output; connect a 1-µF capacitor to DGND. |
| 16 | DGND | power_in | Digital ground; connect to the ADC ground plane. |
| 17 | DVDD | power_in | Digital power supply (3 V to 5 V as printed in the pin table; Recommended Operating Conditions list 2.7 V to 5.25 V). |
| 18 | CLKIN | input | External clock input; connect to DGND for internal oscillator operation. |
| 19 | HV_AVSS | power_in | High-voltage negative analog power supply. |
| 20 | HV_AVDD | power_in | High-voltage positive analog power supply. |
| 21 | NC | unconnected | No connection; electrically float or tie to AGND. |
| 22 | NC | unconnected | No connection; electrically float or tie to AGND. |
| 23 | IDAC2 | output | Current source 2 output. |
| 24 | IDAC1 | output | Current source 1 output. |
| 25 | AINCOM | input | Analog input common (single-ended common input). |
| 26 | AIN0 | input | Analog input 0. |
| 27 | AIN1 | input | Analog input 1. |
| 28 | GPIO3 | bidirectional | General-purpose input/output 3. |
| 29 | GPIO2 | bidirectional | General-purpose input/output 2. |
| 30 | REFN1/GPIO1 | bidirectional | Reference input 1 negative and general-purpose input/output 1. |
| 31 | REFP1/GPIO0 | bidirectional | Reference input 1 positive and general-purpose input/output 0. |
| 32 | REFN0 | input | Reference input 0 negative. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | ADC/DAC/Data Conversion |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute maximum: HV_AVDD to HV_AVSS | -0.3 | 38 | V | 5 | |||
| Absolute maximum: HV_AVSS to AGND | -19 | 0.3 | V | 5 | |||
| Absolute maximum: AVDD to AGND | -0.3 | 6 | V | 5 | |||
| Absolute maximum: DVDD to DGND | -0.3 | 6 | V | 5 | |||
| Absolute maximum: AGND to DGND | -0.1 | 0.1 | V | 5 | |||
| Absolute maximum: continuous input current | -10 | 10 | mA | Continuous | 5 | ||
| Absolute maximum: junction temperature | TJ | 150 | °C | 5 | |||
| Absolute maximum: storage temperature | Tstg | -60 | 150 | °C | 5 | ||
| HV_AVDD to HV_AVSS supply | 10 | 36 | V | 6 | |||
| HV_AVSS to AGND supply | -18 | 0 | V | 6 | |||
| HV_AVDD to AGND supply | 5 | 36 | V | 6 | |||
| Low-voltage analog power supply AVDD to AGND | 4.75 | 5 | 5.25 | V | 6 | ||
| Digital power supply DVDD to DGND | 2.7 | 5.25 | V | 6 | |||
| Differential input voltage range | VIN | -20 | 20 | V | VIN = VAINP, VAINN | 6 | |
| Reference voltage input | VREF | 0.9 | V | VREF = V(REFPx), V(REFNx) | 6 | ||
| External clock frequency, data rate < 40000 SPS | f(CLK) | 1 | 7.3728 | 8 | MHz | Data rate < 40000 SPS | 6 |
| External clock frequency, data rate = 40000 SPS | f(CLK) | 1 | 10.24 | 10.75 | MHz | Data rate = 40000 SPS | 6 |
| External clock duty cycle | 40 | 60 | % | 6 | |||
| Operating ambient temperature | TA | -45 | 125 | °C | 6 | ||
| Absolute input current | -15 | 0.5 | 15 | nA | V(AINx) = 0 V, TA ≤ 105°C | 7 | |
| Differential input current | -0.1 | 0.1 | nA | VIN = 2.5 V | 7 | ||
| Differential input current, auto-zero mode | -2 | 2 | nA/V | VIN = 2.5 V, auto-zero mode | 7 | ||
| Differential input impedance | 1 | 20 | GΩ | 7 | |||
| Data rate | 2.5 | 40000 | SPS | 7 | |||
| Integral nonlinearity, gain 0.125 to 32 | INL | 2 | 10 | ppmFSR | Gain = 0.125 to 32 | 7 | |
| Integral nonlinearity, gain 64 and 128 | INL | 4 | 12 | ppmFSR | Gain = 64, 128 | 7 | |
| Offset voltage drift, gain 16 to 128 | 10 | 50 | nV/°C | Gain = 16 to 128 | 7 | ||
| Gain error | GE | -0.7 | 0.1 | 0.7 | % | TA = 25°C, all gains | 7 |
| Gain drift | 1 | 4 | ppm/°C | All gains | 7 | ||
| Absolute input current, voltage reference inputs | -250 | 250 | nA | 7 | |||
| Initial error of internal voltage reference | -0.2 | 0.1 | 0.2 | % | TA = 25°C | 8 | |
| Temperature drift of internal voltage reference | 3 | 10 | ppm/°C | TA = 0°C to 85°C | 8 | ||
| Temperature drift of internal voltage reference | 7 | 20 | ppm/°C | TA = -40°C to 125°C | 8 | ||
| IDAC output current | -10 | 10 | mA | 8 | |||
| IDAC absolute error | -6 | 0.7 | 6 | % | All currents | 8 | |
| IDAC relative error | -1.5 | 0.1 | 1.5 | % | Equal values | 8 | |
| IDAC relative error | -1 | 1 | % | Unequal values | 8 | ||
| IDAC temperature drift, equal values | 5 | 25 | ppm/°C | Equal values, I ≤ 750 µA | 8 | ||
| Reference monitor low voltage threshold | 0.4 | 0.6 | V | 8 | |||
| Internal oscillator accuracy, data rate < 40000 SPS | -2.5 | 0.5 | 2.5 | % | Data rate < 40000 SPS | 8 | |
| Internal oscillator accuracy, data rate = 40000 SPS | -3.5 | 0.5 | 3.5 | % | Data rate = 40000 SPS | 8 | |
| Digital input leakage | -10 | 10 | µA | 9 | |||
| HV_AVDD, HV_AVSS supply current | IHV_AVDD, IHV_AVSS | 1.1 | 1.8 | mA | 9 | ||
| AVDD supply current | IAVDD | 2.8 | 4.6 | mA | 9 | ||
| DVDD supply current, internal oscillator active | IDVDD | 0.5 | 0.7 | mA | Internal oscillator active | 9 | |
| DVDD supply current, data rate = 40000 SPS | IDVDD | 0.7 | 1 | mA | Data rate = 40000 SPS | 9 | |
| Power dissipation | PD | 49 | 79 | mW | 9 | ||
| Delay time, first SCLK rising edge after CS falling edge | td(CSSC) | 50 | ns | 9 | |||
| Setup time, DIN valid before SCLK falling edge | tsu(DI) | 25 | ns | 9 | |||
| Hold time, DIN valid after SCLK falling edge | th(DI) | 25 | ns | 9 | |||
| SCLK period | tc(SC) | 97 | ns | 9 | |||
| Pulse duration, SCLK high or low | tw(SCH), tw(SCL) | 40 | ns | 9 | |||
| Pulse duration, RESET low | tw(RSTL) | 4 | 1/fCLK | 9 | |||
| Pulse duration, START high | tw(STH) | 4 | 1/fCLK | 9 | |||
| Pulse duration, START low | tw(STL) | 4 | 1/fCLK | 9 | |||
| Setup time, START low or STOP before DRDY falling edge | tsu(STDR) | 100 | 1/fCLK | Continuous mode | 9 | ||
| Hold time, START low or STOP after DRDY falling edge | th(DRSP) | 150 | 1/fCLK | Continuous mode | 9 | ||
| Junction-to-ambient thermal resistance | RθJA | 35.2 | °C/W | 6 | |||
| Junction-to-case (top) thermal resistance | RθJC(top) | 19 | °C/W | 6 | |||
| Junction-to-board thermal resistance | RθJB | 15.8 | °C/W | 6 | |||
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | 8 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
ADS125H02IRHBT - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
ads125h02irhbt-etched.step/ads125h02irhbt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ads125h02irhbt.step/ads125h02irhbt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (88 pp, sha256
a7b83e6da70041ca, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADS125H02IRHBT
**Texas Instruments** · Analog To Digital Converters (ADCs) · VQFN-32-EP(5x5)
ADS125H02IRHBT from Texas Instruments, in a VQFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | REFP0 | input | Reference input 0 positive. |
| 2 | CAPP | output | PGA output P; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN. |
| 3 | CAPN | output | PGA output N; connect a 1-nF C0G dielectric capacitor from CAPP to CAPN. |
| 4 | AVDD | power_in | Low-voltage analog power supply (5 V); recommended range is 4.75 V to 5.25 V. |
| 5 | AGND | power_in | Analog ground; connect to the ADC ground plane. |
| 6 | REFOUT | output | 2.5-V reference output; connect a 10-µF capacitor to AGND. |
| 7 | RESET | input | Reset; active low. |
| 8 | START | input | Conversion start, active high. |
| 9 | CS2 | input | Serial interface chip select 2 to select the PGA for communication. |
| 10 | CS1 | input | Serial interface chip select 1 to select the ADC for communication. |
| 11 | SCLK | input | Serial interface shift clock. |
| 12 | DIN | input | Serial interface data input. |
| 13 | DRDY | output | Data-ready indicator; active low. |
| 14 | DOUT/DRDY | output | Serial interface data output and data-ready indicator (active low). |
| 15 | BYPASS | output | 2-V subregulator output; connect a 1-µF capacitor to DGND. |
| 16 | DGND | power_in | Digital ground; connect to the ADC ground plane. |
| 17 | DVDD | power_in | Digital power supply (3 V to 5 V as printed in the pin table; Recommended Operating Conditions list 2.7 V to 5.25 V). |
| 18 | CLKIN | input | External clock input; connect to DGND for internal oscillator operation. |
| 19 | HV_AVSS | power_in | High-voltage negative analog power supply. |
| 20 | HV_AVDD | power_in | High-voltage positive analog power supply. |
| 21 | NC | unconnected | No connection; electrically float or tie to AGND. |
| 22 | NC | unconnected | No connection; electrically float or tie to AGND. |
| 23 | IDAC2 | output | Current source 2 output. |
| 24 | IDAC1 | output | Current source 1 output. |
| 25 | AINCOM | input | Analog input common (single-ended common input). |
| 26 | AIN0 | input | Analog input 0. |
| 27 | AIN1 | input | Analog input 1. |
| 28 | GPIO3 | bidirectional | General-purpose input/output 3. |
| 29 | GPIO2 | bidirectional | General-purpose input/output 2. |
| 30 | REFN1/GPIO1 | bidirectional | Reference input 1 negative and general-purpose input/output 1. |
| 31 | REFP1/GPIO0 | bidirectional | Reference input 1 positive and general-purpose input/output 0. |
| 32 | REFN0 | input | Reference input 0 negative. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-32-EP(5x5) |
| Category | ADC/DAC/Data Conversion |
| Pins | 33 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute maximum: HV_AVDD to HV_AVSS | | -0.3 | | 38 | V | | 5 |
| Absolute maximum: HV_AVSS to AGND | | -19 | | 0.3 | V | | 5 |
| Absolute maximum: AVDD to AGND | | -0.3 | | 6 | V | | 5 |
| Absolute maximum: DVDD to DGND | | -0.3 | | 6 | V | | 5 |
| Absolute maximum: AGND to DGND | | -0.1 | | 0.1 | V | | 5 |
| Absolute maximum: continuous input current | | -10 | | 10 | mA | Continuous | 5 |
| Absolute maximum: junction temperature | TJ | | | 150 | °C | | 5 |
| Absolute maximum: storage temperature | Tstg | -60 | | 150 | °C | | 5 |
| HV_AVDD to HV_AVSS supply | | 10 | | 36 | V | | 6 |
| HV_AVSS to AGND supply | | -18 | | 0 | V | | 6 |
| HV_AVDD to AGND supply | | 5 | | 36 | V | | 6 |
| Low-voltage analog power supply AVDD to AGND | | 4.75 | 5 | 5.25 | V | | 6 |
| Digital power supply DVDD to DGND | | 2.7 | | 5.25 | V | | 6 |
| Differential input voltage range | VIN | -20 | | 20 | V | VIN = VAINP, VAINN | 6 |
| Reference voltage input | VREF | 0.9 | | | V | VREF = V(REFPx), V(REFNx) | 6 |
| External clock frequency, data rate < 40000 SPS | f(CLK) | 1 | 7.3728 | 8 | MHz | Data rate < 40000 SPS | 6 |
| External clock frequency, data rate = 40000 SPS | f(CLK) | 1 | 10.24 | 10.75 | MHz | Data rate = 40000 SPS | 6 |
| External clock duty cycle | | 40 | | 60 | % | | 6 |
| Operating ambient temperature | TA | -45 | | 125 | °C | | 6 |
| Absolute input current | | -15 | 0.5 | 15 | nA | V(AINx) = 0 V, TA ≤ 105°C | 7 |
| Differential input current | | -0.1 | | 0.1 | nA | VIN = 2.5 V | 7 |
| Differential input current, auto-zero mode | | -2 | | 2 | nA/V | VIN = 2.5 V, auto-zero mode | 7 |
| Differential input impedance | | 1 | 20 | | GΩ | | 7 |
| Data rate | | 2.5 | | 40000 | SPS | | 7 |
| Integral nonlinearity, gain 0.125 to 32 | INL | | 2 | 10 | ppmFSR | Gain = 0.125 to 32 | 7 |
| Integral nonlinearity, gain 64 and 128 | INL | | 4 | 12 | ppmFSR | Gain = 64, 128 | 7 |
| Offset voltage drift, gain 16 to 128 | | | 10 | 50 | nV/°C | Gain = 16 to 128 | 7 |
| Gain error | GE | -0.7 | 0.1 | 0.7 | % | TA = 25°C, all gains | 7 |
| Gain drift | | | 1 | 4 | ppm/°C | All gains | 7 |
| Absolute input current, voltage reference inputs | | -250 | | 250 | nA | | 7 |
| Initial error of internal voltage reference | | -0.2 | 0.1 | 0.2 | % | TA = 25°C | 8 |
| Temperature drift of internal voltage reference | | | 3 | 10 | ppm/°C | TA = 0°C to 85°C | 8 |
| Temperature drift of internal voltage reference | | | 7 | 20 | ppm/°C | TA = -40°C to 125°C | 8 |
| IDAC output current | | -10 | | 10 | mA | | 8 |
| IDAC absolute error | | -6 | 0.7 | 6 | % | All currents | 8 |
| IDAC relative error | | -1.5 | 0.1 | 1.5 | % | Equal values | 8 |
| IDAC relative error | | -1 | | 1 | % | Unequal values | 8 |
| IDAC temperature drift, equal values | | | 5 | 25 | ppm/°C | Equal values, I ≤ 750 µA | 8 |
| Reference monitor low voltage threshold | | | 0.4 | 0.6 | V | | 8 |
| Internal oscillator accuracy, data rate < 40000 SPS | | -2.5 | 0.5 | 2.5 | % | Data rate < 40000 SPS | 8 |
| Internal oscillator accuracy, data rate = 40000 SPS | | -3.5 | 0.5 | 3.5 | % | Data rate = 40000 SPS | 8 |
| Digital input leakage | | -10 | | 10 | µA | | 9 |
| HV_AVDD, HV_AVSS supply current | IHV_AVDD, IHV_AVSS | | 1.1 | 1.8 | mA | | 9 |
| AVDD supply current | IAVDD | | 2.8 | 4.6 | mA | | 9 |
| DVDD supply current, internal oscillator active | IDVDD | | 0.5 | 0.7 | mA | Internal oscillator active | 9 |
| DVDD supply current, data rate = 40000 SPS | IDVDD | | 0.7 | 1 | mA | Data rate = 40000 SPS | 9 |
| Power dissipation | PD | | 49 | 79 | mW | | 9 |
| Delay time, first SCLK rising edge after CS falling edge | td(CSSC) | 50 | | | ns | | 9 |
| Setup time, DIN valid before SCLK falling edge | tsu(DI) | 25 | | | ns | | 9 |
| Hold time, DIN valid after SCLK falling edge | th(DI) | 25 | | | ns | | 9 |
| SCLK period | tc(SC) | 97 | | | ns | | 9 |
| Pulse duration, SCLK high or low | tw(SCH), tw(SCL) | 40 | | | ns | | 9 |
| Pulse duration, RESET low | tw(RSTL) | 4 | | | 1/fCLK | | 9 |
| Pulse duration, START high | tw(STH) | 4 | | | 1/fCLK | | 9 |
| Pulse duration, START low | tw(STL) | 4 | | | 1/fCLK | | 9 |
| Setup time, START low or STOP before DRDY falling edge | tsu(STDR) | 100 | | | 1/fCLK | Continuous mode | 9 |
| Hold time, START low or STOP after DRDY falling edge | th(DRSP) | 150 | | | 1/fCLK | Continuous mode | 9 |
| Junction-to-ambient thermal resistance | RθJA | | 35.2 | | °C/W | | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) | | 19 | | °C/W | | 6 |
| Junction-to-board thermal resistance | RθJB | | 15.8 | | °C/W | | 6 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) | | 8 | | °C/W | | 6 |
## CAD (KiCad official)
- Symbol: `ADS125H02IRHBT`
- Footprint: `Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm`
- 3D model: VQFN-32-EP(5x5) (KiCad packages3D, STEP)
- 3D model files: `ads125h02irhbt-etched.step` / `ads125h02irhbt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ads125h02irhbt.step` / `ads125h02irhbt.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/ads125h02.pdf) (88 pp, sha256 `a7b83e6da70041ca`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ads125h02irhbt-datasheet.pdf)