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docs ads1252u: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
viewers ads1252u: viewers · Ray 1mo ago
ads1252u-etched.fit.json ads1252u: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1252u-etched.glb ads1252u: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1252u-etched.step ads1252u: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray 1mo ago
ads1252u.glb Publish 0.1.0 · Ray 1mo ago
ads1252u.kicad_mod Publish 0.1.0 · Ray 1mo ago
ads1252u.kicad_sym Publish 0.1.0 · Ray 1mo ago
ads1252u.lbr Publish 0.1.0 · Ray 1mo ago
ads1252u.step Publish 0.1.0 · Ray 1mo ago
package.json ads1252u: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
page.json ads1252u: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray 1mo ago
README.md Initial commit: component/ads1252u · Ray 1mo ago

ADS1252U

Texas Instruments · Analog To Digital Converters (ADC) · SOIC-8

ADS1252U from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 +VIN input Positive input of the differential analog input pair, rated ±100 mA momentary / ±10 mA continuous, voltage range GND - 0.3 V to VDD + 0.3 V.
2 -VIN input Negative input of the differential analog input pair, rated ±100 mA momentary / ±10 mA continuous, voltage range GND - 0.3 V to VDD + 0.3 V.
3 +VDD power_in Single +5 V power supply input, operating range +4.75 V to +5.25 V, quiescent current 8-10 mA.
4 CLK input Device system clock input, CMOS-compatible Schmitt-trigger input, maximum 16 MHz.
5 DOUT/DRDY output Serial data output / data-ready indicator; logic LOW indicates new output word available from data output register, data shifts out on rising edge of SCLK.
6 SCLK input Serial clock input, CMOS-compatible Schmitt-trigger, independent of CLK, maximum 16 MHz; holding HIGH initiates modulator reset for converter synchronization or power-down mode.
7 GND power_in Ground / signal reference, must connect to analog ground plane per layout guidelines.
8 VREF power_in Reference voltage input, range 0.5 V to VDD, typical 4.096 V, average load current 220 µA at 16 MHz system clock.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Data Acquisition
Pins 8

CAD (KiCad official)

  • Symbol: ADS1252U
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: ads1252u-etched.step / ads1252u-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1252u.step / ads1252u.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 df5875bf4636e6e4, retrieved 2026-09-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF