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ADS1191IRSMR

Texas Instruments · Analog Front End (AFEs) · VQFN-32-EP(4x4)

ADS1191IRSMR from Texas Instruments, in a VQFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PGA1N output Differential analog negative output of PGA channel 1.
2 PGA1P output Differential analog positive output of PGA channel 1.
3 IN1N input Differential analog negative input 1; excludes effects of noise, linearity, offset, and gain error.
4 IN1P input Differential analog positive input 1; excludes effects of noise, linearity, offset, and gain error.
5 IN2N input Differential analog negative input 2; excludes effects of noise, linearity, offset, and gain error.
6 IN2P input Differential analog positive input 2; excludes effects of noise, linearity, offset, and gain error.
7 PGA2N output Differential analog negative output of PGA channel 2.
8 PGA2P output Differential analog positive output of PGA channel 2.
9 VREFP bidirectional Positive reference voltage; analog input/output pin.
10 VREFN input Negative reference voltage.
11 VCAP1 passive Analog bypass capacitor connection.
12 AVDD power_in Analog supply; AVDD to AVSS is specified from -0.3 V to +7 V absolute maximum.
13 AVSS power_in Analog ground.
14 CLKSEL input Digital input that selects the master clock source.
15 PWDN/RESET input Power-down and system reset input; active low.
16 START input Digital input to start conversions.
17 CLK input Master clock input.
18 CS input SPI chip select digital input.
19 DIN input SPI serial data input.
20 SCLK input SPI serial clock digital input.
21 DOUT output SPI serial data output.
22 DRDY output Data ready digital output; active low.
23 DVDD power_in Digital power supply; DVDD to DGND is specified from -0.3 V to +7 V absolute maximum.
24 DGND power_in Digital ground.
25 GPIO2/RCLK2 bidirectional General-purpose digital input/output GPIO2.
26 GPIO1/RCLK1 bidirectional General-purpose digital input/output GPIO1.
27 VCAP2 passive Analog bypass capacitor connection.
28 RLDINV input Right leg drive inverting input.
29 RLDIN/RLDREF input Right leg drive input to the MUX and RLD reference.
30 RLDOUT input Right leg drive output pin, listed as an analog input in the datasheet table.
31 IN3P bidirectional Differential analog positive input 3; analog input/output pin.
32 IN3N bidirectional Differential analog negative input 3; analog input/output pin.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-32-EP(4x4)
Category ADC/DAC/Data Conversion
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS -0.3 7 V Over operating free-air temperature range 2
DVDD to DGND -0.3 7 V Over operating free-air temperature range 2
AVSS to DGND -3 0.2 V Over operating free-air temperature range 2
Input current to any pin except supply pins -10 10 mA 2
Input current momentary -100 100 mA Momentary 2
Input current continuous -10 10 mA Continuous 2
Operating temperature range -40 85 °C Industrial-grade devices only 2
Storage temperature range -60 150 °C 2
Maximum junction temperature TJ 150 °C 2
Electrostatic discharge HBM -1000 1000 V JEDEC standard 22, test method A114-C.01, all pins 2
Electrostatic discharge CDM -500 500 V JEDEC standard 22, test method C101, all pins 2
Input bias current -1 1 nA Input = 1.5 V 3
Input bias current -2 2 nA Input = 1.5 V, TA = -40°C to +85°C 3
Data rate DR 125 8000 SPS 3
Input-referred noise 24.6 25 μVPP Gain = 6, 256 points, 0.5 seconds of data 3
Integral nonlinearity INL -1 1 LSB Full-scale with gain = 6, best fit 3
Input-referred offset error -100 100 μV 3
Gain error -0.5 0.5 % of FS Excluding voltage reference error 3
Reference input voltage, AVDD = 3 V VREF 2 2.5 V AVDD = 3 V, VREF = (VREFP, VREFN) 4
Reference input voltage, AVDD = 5 V VREF 2 4 V AVDD = 5 V, VREF = (VREFP, VREFN) 4
Current accuracy (lead-off) -20 20 % 4
Comparator threshold accuracy -30 30 mV 4
VREF accuracy -0.5 0.5 % 4
Test signal voltage -1 1 mV See Register Map section for settings 5
Test signal accuracy -2 2 % 5
Internal oscillator clock frequency accuracy -0.5 0.5 % TA = +25°C 5
Internal oscillator clock frequency accuracy -1.5 1.5 % -40°C ≤ TA ≤ +85°C 5
External clock input frequency fCLK 485 512 562.5 kHz CLKSEL pin = 0, CLK_DIV = 0 5
External clock input frequency fCLK 1.94 2.048 2.25 MHz CLKSEL pin = 0, CLK_DIV = 1 5
Input current IIN -10 10 μA 0 V < VDigitalInput < DVDD 5
Analog supply AVDD 2.7 3 5.25 V AVDD, AVSS 5
Digital supply DVDD 1.7 1.8 3.6 V 5
AVDD, DVDD -2.1 3.6 V 5
Quiescent power dissipation, normal mode 450 495 μW Analog Supply = 3 V, RLD Turned Off 6
Specified temperature range -40 85 °C 6
Junction-to-ambient thermal resistance θJA θJA 33.7 °C/W RSM (QFN) 32-pin package 6
Junction-to-case (top) thermal resistance θJCtop 36.4 °C/W RSM (QFN) 32-pin package 6
Junction-to-board thermal resistance θJB 25.2 °C/W RSM (QFN) 32-pin package 6
Junction-to-top characterization parameter ψJT 0.2 °C/W RSM (QFN) 32-pin package 6
Junction-to-board characterization parameter ψJB 7.4 °C/W RSM (QFN) 32-pin package 6
Junction-to-case (bottom) thermal resistance θJCbot 2.2 °C/W RSM (QFN) 32-pin package 6

CAD (KiCad official)

  • Symbol: ADS1191IRSMR
  • Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
  • 3D model: VQFN-32-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: ads1191irsmr-etched.step / ads1191irsmr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1191irsmr.step / ads1191irsmr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (70 pp, sha256 358207ed2a44fab8, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF