ADS1120IPWR

{
  "slug": "ads1120ipwr",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Analog To Digital Converters (ADC), TSSOP-16. Datasheet-verified pinout, KiCad symbol/footprint/3D.",
  "tags": [
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    "data acquisition",
    "ads1120ipwr",
    "factory-2.0.0",
    "extractor-text"
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    "ads1120ipwr.step",
    "ads1120ipwr.lbr",
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    "docs/ads1120ipwr-datasheet.pdf",
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  "component": {
    "mpn": "ADS1120IPWR",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/ads1120",
    "parts": {
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      "footprint": "ads1120ipwr.kicad_mod",
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      "model_3d_step": "ads1120ipwr-etched.step",
      "model_3d_step_plain": "ads1120ipwr.step",
      "lbr": "ads1120ipwr.lbr"
    },
    "distributor_links": {
      "lcsc": "C84284"
    },
    "pins": [
      {
        "number": "1",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input for SPI communication; keep low when interface is idle."
      },
      {
        "number": "2",
        "name": "CS",
        "type": "input",
        "description": "Chip select input, active low; connect to DGND when not sharing SPI bus."
      },
      {
        "number": "3",
        "name": "CLK",
        "type": "input",
        "description": "External clock source input; connect to DGND to enable internal oscillator."
      },
      {
        "number": "4",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground reference for digital power supply and I/O logic circuits."
      },
      {
        "number": "5",
        "name": "AVSS",
        "type": "power_in",
        "description": "Negative analog power supply reference; range −0.1V to 0.1V relative to DGND in single-supply or ±2.5V in dual-supply operation."
      },
      {
        "number": "6",
        "name": "AIN3/REFN1",
        "type": "input",
        "description": "Analog input 3 or negative reference input 1; internal low-side power switch connected between this pin and AVSS."
      },
      {
        "number": "7",
        "name": "AIN2",
        "type": "input",
        "description": "Analog input 2; accepts differential or single-ended signals within −0.1V to AVDD+0.1V absolute range."
      },
      {
        "number": "8",
        "name": "REFN0",
        "type": "input",
        "description": "Negative reference input 0; differential reference voltage VREF = VREFP0 − VREFN0 must be 0.75V to 2.5V."
      },
      {
        "number": "9",
        "name": "REFP0",
        "type": "input",
        "description": "Positive reference input 0; absolute voltage range VREFN0+0.75V to AVDD+0.1V; internally buffered."
      },
      {
        "number": "10",
        "name": "AIN1",
        "type": "input",
        "description": "Analog input 1; accepts differential or single-ended signals within AVSS−0.1V to AVDD+0.1V absolute range."
      },
      {
        "number": "11",
        "name": "AIN0/REFP1",
        "type": "input",
        "description": "Analog input 0 or positive reference input 1; accepts voltages AVSS−0.1V to AVDD+0.1V; can function as primary ADC input or alternate reference input."
      },
      {
        "number": "12",
        "name": "AVDD",
        "type": "power_in",
        "description": "Positive analog power supply; range 2.3V to 5.5V; decouple with 100nF or larger capacitor to AVSS."
      },
      {
        "number": "13",
        "name": "DVDD",
        "type": "power_in",
        "description": "Positive digital power supply; range 2.3V to 5.5V; decouple with 100nF or larger capacitor to DGND."
      },
      {
        "number": "14",
        "name": "DRDY",
        "type": "output",
        "description": "Data ready output, active low; driven low when new conversion result is ready; remains active driven even when CS is high."
      },
      {
        "number": "15",
        "name": "DOUT/DRDY",
        "type": "tri_state",
        "description": "Serial data output and data ready signal combined, active low; enters high-impedance state when CS is high; MSB output first."
      },
      {
        "number": "16",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input for SPI communication; data latched on SCLK falling edge with 50ns setup and 25ns hold times."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-haiku-4-5-20251001",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [],
        "pages_sent": 81,
        "cost_usd": 0.8884,
        "at": "2026-09-23T11:54:21"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/ads1120",
        "pages": 81,
        "sha256": "c860263ddad0839a",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
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}