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Contents

README

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ADS1120IPWR

Texas Instruments · Analog To Digital Converters (ADC) · TSSOP-16

ADS1120IPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input Serial clock input for SPI communication; keep low when interface is idle.
2 CS input Chip select input, active low; connect to DGND when not sharing SPI bus.
3 CLK input External clock source input; connect to DGND to enable internal oscillator.
4 DGND power_in Digital ground reference for digital power supply and I/O logic circuits.
5 AVSS power_in Negative analog power supply reference; range −0.1V to 0.1V relative to DGND in single-supply or ±2.5V in dual-supply operation.
6 AIN3/REFN1 input Analog input 3 or negative reference input 1; internal low-side power switch connected between this pin and AVSS.
7 AIN2 input Analog input 2; accepts differential or single-ended signals within −0.1V to AVDD+0.1V absolute range.
8 REFN0 input Negative reference input 0; differential reference voltage VREF = VREFP0 − VREFN0 must be 0.75V to 2.5V.
9 REFP0 input Positive reference input 0; absolute voltage range VREFN0+0.75V to AVDD+0.1V; internally buffered.
10 AIN1 input Analog input 1; accepts differential or single-ended signals within AVSS−0.1V to AVDD+0.1V absolute range.
11 AIN0/REFP1 input Analog input 0 or positive reference input 1; accepts voltages AVSS−0.1V to AVDD+0.1V; can function as primary ADC input or alternate reference input.
12 AVDD power_in Positive analog power supply; range 2.3V to 5.5V; decouple with 100nF or larger capacitor to AVSS.
13 DVDD power_in Positive digital power supply; range 2.3V to 5.5V; decouple with 100nF or larger capacitor to DGND.
14 DRDY output Data ready output, active low; driven low when new conversion result is ready; remains active driven even when CS is high.
15 DOUT/DRDY tri_state Serial data output and data ready signal combined, active low; enters high-impedance state when CS is high; MSB output first.
16 DIN input Serial data input for SPI communication; data latched on SCLK falling edge with 50ns setup and 25ns hold times.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Data Acquisition
Pins 16

CAD (KiCad official)

  • Symbol: ADS1120IPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ads1120ipwr-etched.step / ads1120ipwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ads1120ipwr.step / ads1120ipwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (81 pp, sha256 c860263ddad0839a, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF