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ADP7104ARDZ-5.0-R7

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Analog Devices Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOIC-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADP7104ARDZ-5.0-R7

Analog Devices · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOIC-8-EP

ADP7104ARDZ-5.0-R7 from Analog Devices, in a SOIC-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VOUT power_out Regulated output voltage; bypass VOUT to GND with 1 µF or larger capacitor.
2 SENSE/ADJ input For the fixed 5.0 V variant this pin is SENSE, which measures the actual output voltage at the load and feeds it to the error amplifier; place it as close to the load as possible to minimize IR drop effects.
3 GND power_in Ground.
4 NC unconnected No connect; do not connect to this pin.
5 EN/UVLO input Enable input: drive high to turn the regulator on and low to turn it off, tie to VIN for automatic startup; absolute maximum rating is −0.3 V to VIN, and when used as programmable UVLO the thresholds are set by external resistors.
6 GND power_in Ground.
7 PG output Open-drain power-good output that requires an external pull-up to VIN or VOUT and goes low immediately in shutdown, current limit, thermal shutdown, or when VOUT falls below 90% of nominal; leave floating or connect to ground if unused, absolute maximum rating −0.3 V to VIN.
8 VIN power_in Regulator input supply, operating range 3.3 V to 20 V with absolute maximum of +22 V to GND; bypass VIN to GND with 1 µF or larger capacitor.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-8-EP
Category Power Management (PMIC)
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage range VIN 3.3 20 V 3
Operating supply current (ground current) IGND 400 µA IOUT = 100 µA, VIN = 10 V 3
Operating supply current (ground current) IGND 900 µA IOUT = 100 µA, VIN = 10 V, TJ = −40°C to +125°C 3
Operating supply current (ground current) IGND 450 µA IOUT = 10 mA, VIN = 10 V 3
Operating supply current (ground current) IGND 1050 µA IOUT = 10 mA, VIN = 10 V, TJ = −40°C to +125°C 3
Operating supply current (ground current) IGND 750 µA IOUT = 300 mA, VIN = 10 V 3
Operating supply current (ground current) IGND 1400 µA IOUT = 300 mA, VIN = 10 V, TJ = −40°C to +125°C 3
Operating supply current (ground current) IGND 1600 µA IOUT = 500 mA, VIN = 10 V, TJ = −40°C to +125°C 3
Shutdown current IGND-SD 40 50 µA EN = GND, VIN = 12 V 3
Shutdown current IGND-SD 75 µA EN = GND, VIN = 12 V, TJ = −40°C to +125°C 3
Input reverse current IREV-INPUT 0.3 µA EN = GND, VIN = 0 V, VOUT = 20 V 3
Input reverse current IREV-INPUT 5 µA EN = GND, VIN = 0 V, VOUT = 20 V, TJ = −40°C to +125°C 3
Fixed output voltage accuracy VOUT -0.8 0.8 % IOUT = 10 mA 3
Fixed output voltage accuracy VOUT -2 1 % 1 mA < IOUT < 500 mA, VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C 3
Line regulation ∆VOUT/∆VIN -0.015 0.015 %/V VIN = (VOUT + 1 V) to 20 V, TJ = −40°C to +125°C 3
Load regulation ∆VOUT/∆IOUT 0.2 %/A IOUT = 1 mA to 500 mA 3
Load regulation ∆VOUT/∆IOUT 0.75 %/A IOUT = 1 mA to 500 mA, TJ = −40°C to +125°C 3
Dropout voltage VDROPOUT 20 mV IOUT = 10 mA 3
Dropout voltage VDROPOUT 40 mV IOUT = 10 mA, TJ = −40°C to +125°C 3
Dropout voltage VDROPOUT 100 mV IOUT = 150 mA 3
Dropout voltage VDROPOUT 175 mV IOUT = 150 mA, TJ = −40°C to +125°C 3
Dropout voltage VDROPOUT 200 mV IOUT = 300 mA 3
Dropout voltage VDROPOUT 325 mV IOUT = 300 mA, TJ = −40°C to +125°C 3
Dropout voltage VDROPOUT 350 mV IOUT = 500 mA 3
Dropout voltage VDROPOUT 550 mV IOUT = 500 mA, TJ = −40°C to +125°C 3
Current limit threshold ILIMIT 625 775 1000 mA 3
PG output logic high level PGHIGH 1 V IOH < 1 µA 3
PG output logic low level PGLOW 0.4 V IOL < 2 mA 3
PG output threshold, output voltage falling PGFALL -9.2 % 3
PG output threshold, output voltage rising PGRISE -6.5 % 3
Thermal shutdown threshold TSSD 150 °C TJ rising 3
Thermal shutdown hysteresis TSSD-HYS 15 °C 3
UVLO threshold rising UVLORISE 1.18 1.22 1.28 V 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C 4
UVLO threshold falling UVLOFALL 1.13 V 3.3 V ≤ VIN ≤ 20 V, TJ = −40°C to +125°C, 10 kΩ resistor in series with EN pin 4
UVLO hysteresis current UVLOHYS 7.5 9.8 12 µA VEN > 1.25 V, TJ = −40°C to +125°C 4
Output noise OUTNOISE 15 µV rms 10 Hz to 100 kHz, VIN = 8 V, VOUT = 5 V 4
Power supply rejection ratio PSRR 50 dB 100 kHz, VIN = 6 V, VOUT = 5 V 4
Power supply rejection ratio PSRR 60 dB 10 kHz, VIN = 6 V, VOUT = 5 V 4
Minimum input and output capacitance CMIN 0.7 µF TA = −40°C to +125°C 4
Capacitor ESR RESR 0.001 0.2 Ω TA = −40°C to +125°C 4
VIN to GND VIN -0.3 22 V 5
VOUT to GND VOUT -0.3 20 V 5
EN/UVLO to GND (max = VIN) EN/UVLO -0.3 V 5
PG to GND (max = VIN) PG -0.3 V 5
SENSE/ADJ to GND (max = VOUT) SENSE/ADJ -0.3 V 5
Storage temperature range -65 150 °C 5
Operating junction temperature range TJ -40 125 °C 5
Junction-to-ambient thermal resistance, 8-lead SOIC θJA 48.5 °C/W 4-layer board, JEDEC 5
Junction-to-case thermal resistance, 8-lead SOIC θJC 58.4 °C/W 5
Junction-to-board thermal characterization parameter, 8-lead SOIC ΨJB 31.3 °C/W 5

CAD (KiCad official)

  • Symbol: ADP7104ARDZ-5.0-R7
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.29x3mm
  • 3D model: SOIC-8-EP (KiCad packages3D, STEP)
  • 3D model files: adp7104ardz-5-0-r7-etched.step / adp7104ardz-5-0-r7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adp7104ardz-5-0-r7.step / adp7104ardz-5-0-r7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 269a0ae0cec349ea, retrieved 2026-10-09, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF