ADP5074ACPZ-R7

{
  "slug": "adp5074acpz-r7",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices DC-DC Converters, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "power management (pmic)",
    "adp5074acpz-r7",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "adp5074acpz-r7.kicad_sym",
    "adp5074acpz-r7.kicad_mod",
    "adp5074acpz-r7.glb",
    "adp5074acpz-r7.step",
    "adp5074acpz-r7.lbr",
    "docs/hero.png",
    "docs/adp5074acpz-r7-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "adp5074acpz-r7-hero.glb",
    "adp5074acpz-r7-hero.overlay.json",
    "adp5074acpz-r7-etched.glb"
  ],
  "component": {
    "mpn": "ADP5074ACPZ-R7",
    "manufacturer": "Analog Devices",
    "package": "LFCSP-16(3x3)",
    "pin_count": 17,
    "category": "Power Management (PMIC)",
    "subcategory": "DC-DC Converters",
    "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915513779372032",
    "parts": {
      "symbol": "adp5074acpz-r7.kicad_sym",
      "footprint": "adp5074acpz-r7.kicad_mod",
      "model_3d": "adp5074acpz-r7-hero.glb",
      "model_3d_plain": "adp5074acpz-r7-etched.glb",
      "model_3d_step": "adp5074acpz-r7-etched.step",
      "model_3d_step_plain": "adp5074acpz-r7.step",
      "lbr": "adp5074acpz-r7.lbr"
    },
    "distributor_links": {
      "lcsc": "C659272",
      "mouser": "584-ADP5074ACPZ-R7"
    },
    "distributor_check": {
      "checked_at": "2026-10-17T21:14:58Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": null,
        "status": "quota"
      },
      "mouser": {
        "pn": "584-ADP5074ACPZ-R7",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "SW",
        "type": "output",
        "description": "Switching node for the inverting regulator, driven by the integrated main switch."
      },
      {
        "number": "2",
        "name": "SLEW",
        "type": "input",
        "description": "Driver stage slew rate control: leave open for the fastest slew rate (best efficiency), connect to VREG for a normal slew rate, or connect to GND for the slowest slew rate (best noise performance)."
      },
      {
        "number": "3",
        "name": "PWRGD",
        "type": "output",
        "description": "Open-drain power-good output that must be pulled up to VREG with a resistor, providing a high output when power is good."
      },
      {
        "number": "4",
        "name": "SYNC/FREQ",
        "type": "input",
        "description": "Frequency setting and synchronization input: pull high for 2.4 MHz switching, pull low for 1.2 MHz switching, or connect an external clock to synchronize the switching frequency."
      },
      {
        "number": "5",
        "name": "SS",
        "type": "passive",
        "description": "Soft start programming: leave open for the fastest soft start time, or connect a resistor between this pin and GND for a slower soft start time."
      },
      {
        "number": "6",
        "name": "EN",
        "type": "input",
        "description": "Inverting regulator precision enable; the EN pin is compared to an internal precision reference to enable the inverting regulator output."
      },
      {
        "number": "7",
        "name": "COMP",
        "type": "passive",
        "description": "Error amplifier compensation for the inverting regulator; the compensation network connects between this pin and GND."
      },
      {
        "number": "8",
        "name": "FB",
        "type": "input",
        "description": "Feedback input for the inverting regulator; a resistor divider between the negative side of the output capacitor and VREF programs the output voltage."
      },
      {
        "number": "9",
        "name": "VREF",
        "type": "power_in",
        "description": "Inverting regulator reference output; connect a 1.0 µF ceramic filter capacitor between VREF and GND."
      },
      {
        "number": "10",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference for the device."
      },
      {
        "number": "11",
        "name": "VREG",
        "type": "power_out",
        "description": "Internal regulator output; connect a 1.0 µF ceramic filter capacitor between VREG and GND."
      },
      {
        "number": "12",
        "name": "PVIN",
        "type": "power_in",
        "description": "Power input for the inverting regulator."
      },
      {
        "number": "13",
        "name": "AVIN",
        "type": "power_in",
        "description": "System power supply input for the ADP5074."
      },
      {
        "number": "14",
        "name": "NIC",
        "type": "unconnected",
        "description": "No internal connection; for improved thermal performance, connect to the PCB ground plane."
      },
      {
        "number": "15",
        "name": "NIC",
        "type": "unconnected",
        "description": "No internal connection; for improved thermal performance, connect to the PCB ground plane."
      },
      {
        "number": "16",
        "name": "NIC",
        "type": "unconnected",
        "description": "No internal connection; for improved thermal performance, connect to the PCB ground plane."
      },
      {
        "number": "17",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pin numbers, names and functions are taken from the Figure 2 pin configuration and Table 5 pin funct; Datasheet page 4 was not included in the provided text. It is not needed for the pinout, but it was ; Pins 14-16 are NIC (no internal connection) and are typed unconnected. The datasheet says to connect",
          "exposed pad 17 added from the footprint",
          "dropped thermal pad ['EP'] absent from footprint"
        ],
        "pages_sent": 8,
        "cost_usd": 0.0529,
        "at": "2026-10-17T21:13:23"
      },
      "datasheet": {
        "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588915513779372032",
        "pages": 17,
        "sha256": "93ee2210e32b89a7",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 17,
        "described": 17,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3eb81ffac423a66cdcfead8efe56401da171edaf1f2257049aad7b2d3900f6c8",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "adp5074acpz-r7-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "sha256": "52db35bbb885dccafb69b3a1fd41bba6387db46bb437c26cada0c824ffd2762e",
        "checked": "2026-10-17",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}