component
ADP5074ACPZ-R7
Public Made by Adomby adom
Analog Devices DC-DC Converters, LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 16d ago |
| viewers | 16d ago |
| adp5074acpz-r7-etched.glb | 16d ago |
| adp5074acpz-r7-etched.step | 16d ago |
| adp5074acpz-r7-hero.glb | 16d ago |
| adp5074acpz-r7-hero.overlay.json | 16d ago |
| adp5074acpz-r7.glb | 16d ago |
| adp5074acpz-r7.kicad_mod | 16d ago |
| adp5074acpz-r7.kicad_sym | 16d ago |
| adp5074acpz-r7.lbr | 16d ago |
| adp5074acpz-r7.step | 16d ago |
| package.json | 16d ago |
| page.json | 16d ago |
| README.md | 16d ago |
ADP5074ACPZ-R7
Analog Devices · DC-DC Converters · LFCSP-16(3x3)
ADP5074ACPZ-R7 from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switching node for the inverting regulator, driven by the integrated main switch. |
| 2 | SLEW | input | Driver stage slew rate control: leave open for the fastest slew rate (best efficiency), connect to VREG for a normal slew rate, or connect to GND for the slowest slew rate (best noise performance). |
| 3 | PWRGD | output | Open-drain power-good output that must be pulled up to VREG with a resistor, providing a high output when power is good. |
| 4 | SYNC/FREQ | input | Frequency setting and synchronization input: pull high for 2.4 MHz switching, pull low for 1.2 MHz switching, or connect an external clock to synchronize the switching frequency. |
| 5 | SS | passive | Soft start programming: leave open for the fastest soft start time, or connect a resistor between this pin and GND for a slower soft start time. |
| 6 | EN | input | Inverting regulator precision enable; the EN pin is compared to an internal precision reference to enable the inverting regulator output. |
| 7 | COMP | passive | Error amplifier compensation for the inverting regulator; the compensation network connects between this pin and GND. |
| 8 | FB | input | Feedback input for the inverting regulator; a resistor divider between the negative side of the output capacitor and VREF programs the output voltage. |
| 9 | VREF | power_in | Inverting regulator reference output; connect a 1.0 µF ceramic filter capacitor between VREF and GND. |
| 10 | GND | power_in | Ground reference for the device. |
| 11 | VREG | power_out | Internal regulator output; connect a 1.0 µF ceramic filter capacitor between VREG and GND. |
| 12 | PVIN | power_in | Power input for the inverting regulator. |
| 13 | AVIN | power_in | System power supply input for the ADP5074. |
| 14 | NIC | unconnected | No internal connection; for improved thermal performance, connect to the PCB ground plane. |
| 15 | NIC | unconnected | No internal connection; for improved thermal performance, connect to the PCB ground plane. |
| 16 | NIC | unconnected | No internal connection; for improved thermal performance, connect to the PCB ground plane. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-16(3x3) |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage range | VIN | 2.85 | 15 | V | PVIN, AVIN | 3 | |
| Operating quiescent current, PVIN, AVIN (total) | IQ | 1.8 | 4 | mA | No switching, EN = high, PVIN = AVIN = 5 V | 3 | |
| Shutdown current | ISHDN | 5 | 10 | µA | No switching, EN = low, PVIN = AVIN = 5 V, −40°C ≤ TJ ≤ +85°C | 3 | |
| System UVLO threshold, AVIN rising | VUVLO_RISING | 2.8 | 2.85 | V | 3 | ||
| System UVLO threshold, AVIN falling | VUVLO_FALLING | 2.5 | 2.55 | V | 3 | ||
| Switching frequency | fSW | 1.13 | 1.2 | 1.27 | MHz | SYNC/FREQ = low | 3 |
| Switching frequency | fSW | 2.24 | 2.4 | 2.56 | MHz | SYNC/FREQ = high (connect to VREG) | 3 |
| Input clock range | fSYNC | 1 | 2.6 | MHz | 3 | ||
| Input clock minimum on pulse width | tSYNC_MIN_ON | 100 | ns | 3 | |||
| Input clock minimum off pulse width | tSYNC_MIN_OFF | 100 | ns | 3 | |||
| Input clock high logic | VH (SYNC) | 1.3 | V | 3 | |||
| Input clock low logic | VL (SYNC) | 0.4 | V | 3 | |||
| Precision enable high level threshold | VTH_H | 1.125 | 1.15 | 1.175 | V | 3 | |
| Precision enable low level threshold | VTH_L | 1.025 | 1.05 | 1.075 | V | 3 | |
| Shutdown mode threshold | VTH_S | 0.4 | V | Internal circuitry disabled to achieve ISHDN | 3 | ||
| Reference voltage accuracy | -0.5 | 0.5 | % | TJ = 25°C | 3 | ||
| Reference voltage accuracy | -1.5 | 1.5 | % | TJ = −40°C to +125°C | 3 | ||
| Feedback voltage accuracy | -0.5 | 0.5 | % | TJ = 25°C | 3 | ||
| Feedback voltage accuracy | -1.5 | 1.5 | % | TJ = −40°C to +125°C | 3 | ||
| Power-good FET maximum drain source voltage | VDS_PG(MAX) | 5.5 | V | 3 | |||
| Error amplifier transconductance | gM | 270 | 300 | 330 | µA/V | 4 | |
| Power FET maximum drain source voltage | VDS (MAX) | 39 | V | 4 | |||
| Current-limit threshold | ILIM | 2.4 | 2.75 | 3.2 | A | 4 | |
| Absolute max, PVIN and AVIN voltage | PVIN, AVIN | -0.3 | 18 | V | 5 | ||
| Absolute max, SW voltage | SW | -40 | 0.3 | V | Relative to PVIN (PVIN − 40 V to PVIN + 0.3 V) | 5 | |
| Absolute max, GND voltage | GND | -0.3 | 0.3 | V | 5 | ||
| Absolute max, VREG voltage | VREG | -0.3 | 6 | V | Lower of AVIN + 0.3 V or +6 V | 5 | |
| Absolute max, EN, FB, SYNC/FREQ, PWRGD voltage | -0.3 | 6 | V | EN, FB, SYNC/FREQ, PWRGD | 5 | ||
| Absolute max, COMP, SLEW, SS, VREF voltage | -0.3 | V | Maximum is VREG + 0.3 V | 5 | |||
| Operating junction temperature range | TJ | -40 | 125 | °C | 5 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 5 | ||
| Internal regulator output voltage | VREG | 4.25 | V | 3 | |||
| Reference voltage | VREF | 1.6 | V | 3 | |||
| Feedback voltage | VREF − VFB | 0.8 | V | 3 | |||
| Feedback bias current | IFB | 0.1 | µA | 3 | |||
| Overvoltage protection threshold | VOV | 0.74 | V | At the FB pin after soft start is complete | 3 | ||
| Power-good threshold (good) | VPG (GOOD) | 0.7 | V | VREF − VFB ≥ VPG (GOOD) | 3 | ||
| Power-good threshold (bad) | VPG (BAD) | 0.68 | V | VREF − VFB ≤ VPG (BAD) | 3 | ||
| Power-good FET on resistance | RDS_PG (ON) | 28 | Ω | 3 | |||
| Power-good supply voltage | VPG(SUPPLY) | 1.4 | V | Voltage required on PVIN pin for power-good FET to pull down | 3 | ||
| Load regulation | ∆(VREF − VFB)/∆ILOAD | 0.0006 | %/A | ILOAD = 20 mA to 1500 mA (regulator not in skip mode) | 3 | ||
| Line regulation | ∆(VREF − VFB)/∆VVIN | 0.02 | %/V | VVIN = 2.85 V to 14.5 V, ILOAD = 15 mA (regulator not in skip mode) | 3 | ||
| Power FET on resistance | RDS (ON) | 200 | mΩ | VIN = 5 V | 4 | ||
| Minimum on time | 55 | ns | 4 | ||||
| Minimum off time | 50 | ns | 4 | ||||
| Soft start timer | tSS | 4 | ms | SS = open | 4 | ||
| Soft start timer | tSS | 32 | ms | SS resistor = 50 kΩ to GND | 4 | ||
| Thermal shutdown threshold | TSHDN | 150 | °C | 4 | |||
| Thermal shutdown hysteresis | THYS | 15 | °C | 4 | |||
| Precision enable pull-down resistance | REN | 1.48 | MΩ | 3 | |||
| System UVLO hysteresis | VHYS | 0.25 | V | 3 | |||
| Junction-to-ambient thermal resistance, 16-lead LFCSP | θJA | 75.01 | °C/W | 4-layer PCB with thermal vias | 5 | ||
| Junction-to-case thermal resistance, 16-lead LFCSP | θJC | 55.79 | °C/W | Measured at top of package | 5 | ||
| Junction-to-top characterization parameter, 16-lead LFCSP | ΨJT | 0.95 | °C/W | 4-layer PCB with thermal vias | 5 |
CAD (KiCad official)
- Symbol:
ADP5074ACPZ-R7 - Footprint:
Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm - 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
- 3D model files:
adp5074acpz-r7-etched.step/adp5074acpz-r7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adp5074acpz-r7.step/adp5074acpz-r7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (17 pp, sha256
93ee2210e32b89a7, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).