# S32K344

ASIL D Lockstep Core Arm Cortex-M7 4MB Automotive MCU, 160 MHz, CAN-FD, Ethernet, ADC

| Field | Value |
|-------|-------|
| Manufacturer | NXP Semiconductors |
| Package | HDQFP-172 |
| Pins | 172 |
| Datasheet | [PDF](https://www.nxp.com/docs/en/data-sheet/S32K3xx.pdf) |

## Pin Table

| # | Name | Type | Group | Description |
|---|------|------|-------|-------------|
| 1 | PTA0 | bidirectional | PORT A | GPIO / LPUART0_CTS / LPSPI0_PCS1 / TRGMUX_OUT3. General-purpose I/O with LPUART0 clear-to-send and LPSPI0 chip select... |
| 2 | PTA1 | bidirectional | PORT A | GPIO / LPUART0_RTS / LPSPI0_SOUT / FLEXIO_D2. General-purpose I/O with LPUART0 request-to-send and FlexIO channel 2. |
| 3 | PTA2 | bidirectional | PORT A | GPIO / LPUART0_TX / eMIOS0_CH0. LPUART0 transmit data or eMIOS0 timer channel 0 (IC/OC/PWM). |
| 4 | PTA3 | bidirectional | PORT A | GPIO / LPUART0_RX / eMIOS0_CH1. LPUART0 receive data or eMIOS0 timer channel 1 (IC/OC/PWM). |
| 5 | PTA4 | bidirectional | PORT A | GPIO / eMIOS1_CH0 / LPSPI3_PCS3. Timer channel or SPI chip select alternate. |
| 6 | PTA5 | bidirectional | PORT A | GPIO / eMIOS1_CH1 / LPSPI3_PCS2. Timer channel or SPI chip select alternate. |
| 7 | PTA6 | bidirectional | PORT A | GPIO / LPUART1_CTS / eMIOS0_CH2 / LPSPI1_PCS1. LPUART1 flow control or timer. |
| 8 | PTA7 | bidirectional | PORT A | GPIO / LPUART1_RTS / eMIOS0_CH3 / LPSPI1_PCS0. LPUART1 flow control or SPI chip select. |
| 9 | PTA8 | bidirectional | PORT A | GPIO / LPUART1_TX / eMIOS0_CH4 / LPSPI1_SOUT. LPUART1 transmit or SPI data out. |
| 10 | PTA9 | bidirectional | PORT A | GPIO / LPUART1_RX / eMIOS0_CH5 / LPSPI1_SIN. LPUART1 receive or SPI data in. |
| 12 | PTA10 | bidirectional | PORT A | GPIO / eMIOS0_CH6 / LPSPI1_SCK. Timer channel or SPI clock alternate function. |
| 13 | PTA11 | bidirectional | PORT A | GPIO / eMIOS0_CH7 / LPI2C0_SDA. Timer channel or I2C data line. Requires external 4.7kΩ pull-up for I2C. |
| 23 | PTA14 | bidirectional | PORT A | GPIO / eMIOS1_CH2 / LPSPI1_PCS2. Adjacent to FXOSC — limit to static GPIO operation to avoid clock jitter degradation. |
| 25 | PTA15 | bidirectional | PORT A | GPIO / LPUART2_TX / eMIOS1_CH3. LPUART2 transmit or timer channel. |
| 26 | PTA16 | bidirectional | PORT A | GPIO / LPUART2_RX / eMIOS1_CH4. LPUART2 receive or timer channel. |
| 27 | PTA17 | bidirectional | PORT A | GPIO / eMIOS1_CH5 / FlexCAN0_TX. Timer or CAN bus transmit. |
| 28 | PTA24 | bidirectional | PORT A | GPIO / eMIOS1_CH6 / FlexCAN0_RX. Timer or CAN bus receive. |
| 29 | PTA25 | bidirectional | PORT A | GPIO / eMIOS1_CH7 / LPUART2_CTS. Timer or UART flow control. |
| 30 | PTA26 | bidirectional | PORT A | GPIO / eMIOS1_CH8 / LPUART2_RTS. Timer or UART flow control. |
| 31 | PTA27 | bidirectional | PORT A | GPIO / eMIOS1_CH9 / LPI2C0_SCL. Timer or I2C clock. Requires 4.7kΩ external pull-up for I2C. |
| 32 | PTA28 | bidirectional | PORT A | GPIO / eMIOS1_CH10 / FlexCAN1_TX. Timer or CAN-FD bus transmit. |
| 33 | PTA29 | bidirectional | PORT A | GPIO / eMIOS1_CH11 / FlexCAN1_RX. Timer or CAN-FD bus receive. |
| 34 | PTA30 | bidirectional | PORT A | GPIO / eMIOS1_CH12 / LPSPI0_PCS0. Timer or SPI chip select. |
| 35 | PTA31 | bidirectional | PORT A | GPIO / eMIOS1_CH13 / LPSPI0_SCK. Timer or SPI clock. |
| 36 | PTB0 | bidirectional | PORT B | GPIO / eMIOS1_CH14 / LPSPI0_SOUT. Timer or SPI data output. |
| 39 | PTB1 | bidirectional | PORT B | GPIO / eMIOS1_CH15 / LPSPI0_SIN. Timer or SPI data input. |
| 40 | PTB2 | bidirectional | PORT B | GPIO / eMIOS1_CH16 / LPUART3_TX. Timer or LPUART3 transmit. |
| 41 | PTB3 | bidirectional | PORT B | GPIO / eMIOS1_CH17 / LPUART3_RX. Timer or LPUART3 receive. |
| 42 | PTB4 | bidirectional | PORT B | GPIO / LPI2C1_SDA / eMIOS1_CH18. I2C1 data or timer. Requires 4.7kΩ pull-up for I2C. |
| 43 | PTB5 | bidirectional | PORT B | GPIO / LPI2C1_SCL / eMIOS1_CH19. I2C1 clock or timer. Requires 4.7kΩ pull-up for I2C. |
| 44 | PTB6 | bidirectional | PORT B | GPIO / FlexCAN2_TX / eMIOS1_CH20. CAN-FD bus 2 transmit or timer. |
| 45 | PTB7 | bidirectional | PORT B | GPIO / FlexCAN2_RX / eMIOS1_CH21. CAN-FD bus 2 receive or timer. |
| 46 | PTB8 | bidirectional | PORT B | GPIO / LPUART4_TX / eMIOS0_CH8. LPUART4 transmit or timer. |
| 47 | PTB9 | bidirectional | PORT B | GPIO / LPUART4_RX / eMIOS0_CH9. LPUART4 receive or timer. |
| 48 | PTB10 | bidirectional | PORT B | GPIO / eMIOS0_CH10 / LPSPI2_SCK. Timer or LPSPI2 clock. |
| 49 | PTB11 | bidirectional | PORT B | GPIO / eMIOS0_CH11 / LPSPI2_SIN. Timer or LPSPI2 data in. |
| 50 | PTB12 | bidirectional | PORT B | GPIO / eMIOS0_CH12 / LPSPI2_SOUT. Timer or LPSPI2 data out. |
| 51 | PTB13 | bidirectional | PORT B | GPIO / eMIOS0_CH13 / LPSPI2_PCS0. Timer or LPSPI2 chip select. |
| 52 | PTB14 | bidirectional | PORT B | GPIO / FlexCAN3_TX / eMIOS0_CH14. CAN-FD bus 3 transmit or timer. |
| 53 | PTB15 | bidirectional | PORT B | GPIO / FlexCAN3_RX / eMIOS0_CH15. CAN-FD bus 3 receive or timer. |
| 54 | PTB16 | bidirectional | PORT B | GPIO / LPUART5_TX / eMIOS0_CH16. LPUART5 transmit or timer. |
| 55 | PTB17 | bidirectional | PORT B | GPIO / LPUART5_RX / eMIOS0_CH17. LPUART5 receive or timer. |
| 56 | PTB18 | bidirectional | PORT B | GPIO / SAI0_BCLK / eMIOS0_CH18. Synchronous Audio Interface 0 bit clock or timer. |
| 61 | PTB19 | bidirectional | PORT B | GPIO / SAI0_D0 / eMIOS0_CH19. SAI0 data line 0 or timer. |
| 62 | PTB20 | bidirectional | PORT B | GPIO / SAI0_SYNC. SAI0 frame sync signal. |
| 63 | PTB21 | bidirectional | PORT B | GPIO / SAI0_MCLK. SAI0 master clock output. |
| 64 | PTB22 | bidirectional | PORT B | GPIO / LPUART6_TX / eMIOS0_CH20. LPUART6 transmit or timer. |
| 65 | PTB23 | bidirectional | PORT B | GPIO / LPUART6_RX / eMIOS0_CH21. LPUART6 receive or timer. |
| 66 | PTB24 | bidirectional | PORT B | GPIO / FlexCAN4_TX / eMIOS0_CH22. CAN-FD bus 4 transmit or timer. |
| 67 | PTB25 | bidirectional | PORT B | GPIO / FlexCAN4_RX / eMIOS0_CH23. CAN-FD bus 4 receive or timer. |
| 68 | PTB26 | bidirectional | PORT B | GPIO / LPUART7_TX / FLEXIO_D0. LPUART7 transmit or FlexIO channel. |
| 69 | PTB27 | bidirectional | PORT B | GPIO / LPUART7_RX / FLEXIO_D1. LPUART7 receive or FlexIO channel. |
| 70 | PTB28 | bidirectional | PORT B | GPIO / FLEXIO_D2 / eMIOS2_CH0. FlexIO channel or eMIOS2 timer. |
| 71 | PTB29 | bidirectional | PORT B | GPIO / FLEXIO_D3 / eMIOS2_CH1. FlexIO channel or eMIOS2 timer. |
| 72 | PTB30 | bidirectional | PORT B | GPIO / FLEXIO_D4 / eMIOS2_CH2. FlexIO channel or eMIOS2 timer. |
| 73 | PTB31 | bidirectional | PORT B | GPIO / FLEXIO_D5 / eMIOS2_CH3. FlexIO channel or eMIOS2 timer. |
| 74 | PTC0 | bidirectional | PORT C | GPIO / ADC0_S8 / eMIOS2_CH4. 12-bit ADC0 standard channel 8 (0–5.5V input range) or timer. |
| 75 | PTC1 | bidirectional | PORT C | GPIO / ADC0_S9 / eMIOS2_CH5. ADC0 channel 9 or timer. |
| 76 | PTC2 | bidirectional | PORT C | GPIO / ADC0_S10 / eMIOS2_CH6. ADC0 channel 10 or timer. |
| 79 | PTC3 | bidirectional | PORT C | GPIO / ADC0_S11 / eMIOS2_CH7. ADC0 channel 11 or timer. |
| 80 | PTC4 | bidirectional | PORT C | GPIO / ADC0_S12 / LPUART8_TX. ADC0 channel 12 or LPUART8 transmit. |
| 81 | PTC5 | bidirectional | PORT C | GPIO / ADC0_S13 / LPUART8_RX. ADC0 channel 13 or LPUART8 receive. |
| 82 | PTC6 | bidirectional | PORT C | GPIO / ADC0_S14 / FlexCAN5_TX. ADC0 channel 14 or CAN-FD bus 5 transmit. |
| 83 | PTC7 | bidirectional | PORT C | GPIO / ADC0_S15 / FlexCAN5_RX. ADC0 channel 15 or CAN-FD bus 5 receive. |
| 84 | PTC8 | bidirectional | PORT C | GPIO / ADC1_S0 / eMIOS2_CH8. 12-bit ADC1 channel 0 or eMIOS2 timer. |
| 85 | PTC9 | bidirectional | PORT C | GPIO / ADC1_S1 / eMIOS2_CH9. ADC1 channel 1 or timer. |
| 86 | PTC10 | bidirectional | PORT C | GPIO / ADC1_S2 / eMIOS2_CH10. ADC1 channel 2 or timer. |
| 87 | PTC11 | bidirectional | PORT C | GPIO / ADC1_S3 / eMIOS2_CH11. ADC1 channel 3 or timer. |
| 88 | PTC12 | bidirectional | PORT C | GPIO / ADC1_S4 / LPSPI3_SCK. ADC1 channel 4 or LPSPI3 clock. |
| 89 | PTC13 | bidirectional | PORT C | GPIO / ADC1_S5 / LPSPI3_SIN. ADC1 channel 5 or LPSPI3 data in. |
| 90 | PTC14 | bidirectional | PORT C | GPIO / ADC1_S6 / LPSPI3_SOUT. ADC1 channel 6 or LPSPI3 data out. |
| 91 | PTC15 | bidirectional | PORT C | GPIO / ADC1_S7 / LPSPI3_PCS0. ADC1 channel 7 or LPSPI3 chip select. |
| 92 | PTC16 | bidirectional | PORT C | GPIO / ADC1_S8 / LPUART9_TX. ADC1 channel 8 or LPUART9 transmit. |
| 93 | PTC17 | bidirectional | PORT C | GPIO / ADC1_S9 / LPUART9_RX. ADC1 channel 9 or LPUART9 receive. |
| 94 | PTC18 | bidirectional | PORT C | GPIO / ADC1_S10 / LPUART10_TX. ADC1 channel 10 or LPUART10 transmit. |
| 95 | PTC19 | bidirectional | PORT C | GPIO / ADC1_S11 / LPUART10_RX. ADC1 channel 11 or LPUART10 receive. |
| 96 | PTC20 | bidirectional | PORT C | GPIO / ADC1_S12 / eMIOS2_CH12. ADC1 channel 12 or timer. |
| 97 | PTC21 | bidirectional | PORT C | GPIO / ADC1_S13 / eMIOS2_CH13. ADC1 channel 13 or timer. |
| 98 | PTC22 | bidirectional | PORT C | GPIO / ADC1_S14 / eMIOS2_CH14. ADC1 channel 14 or timer. |
| 99 | PTC23 | bidirectional | PORT C | GPIO / ADC1_S15 / eMIOS2_CH15. ADC1 channel 15 or timer. |
| 100 | PTC24 | bidirectional | PORT C | GPIO / eMIOS2_CH16 / LPCMP0_IN0. Timer or low-power comparator 0 non-inverting input. |
| 101 | PTC25 | bidirectional | PORT C | GPIO / eMIOS2_CH17 / LPCMP0_IN1. Timer or low-power comparator 0 inverting input. |
| 102 | PTC26 | bidirectional | PORT C | GPIO / eMIOS2_CH18 / LPCMP1_IN0. Timer or low-power comparator 1 non-inverting input. |
| 103 | PTC27 | bidirectional | PORT C | GPIO / eMIOS2_CH19 / LPCMP1_IN1. Timer or low-power comparator 1 inverting input. |
| 104 | PTC28 | bidirectional | PORT C | GPIO / eMIOS2_CH20 / LPCMP2_IN0. Timer or low-power comparator 2 input. |
| 109 | PTC29 | bidirectional | PORT C | GPIO / eMIOS2_CH21 / LPCMP2_IN1. Timer or low-power comparator 2 input. |
| 110 | PTC30 | bidirectional | PORT C | GPIO / eMIOS2_CH22. Timer channel. |
| 111 | PTC31 | bidirectional | PORT C | GPIO / eMIOS2_CH23. Timer channel. |
| 112 | PTD0 | bidirectional | PORT D | GPIO / FLEXIO_D6 / LPUART11_TX. FlexIO channel 6 or LPUART11 transmit. |
| 113 | PTD1 | bidirectional | PORT D | GPIO / FLEXIO_D7 / LPUART11_RX. FlexIO channel 7 or LPUART11 receive. |
| 114 | PTD2 | bidirectional | PORT D | GPIO / FLEXIO_D8 / LPUART12_TX. FlexIO channel 8 or LPUART12 transmit. |
| 115 | PTD3 | bidirectional | PORT D | GPIO / FLEXIO_D9 / LPUART12_RX. FlexIO channel 9 or LPUART12 receive. |
| 116 | PTD4 | bidirectional | PORT D | GPIO / FLEXIO_D10 / LPUART13_TX. FlexIO channel 10 or LPUART13 transmit. |
| 117 | PTD5 | bidirectional | PORT D | GPIO / FLEXIO_D11 / LPUART13_RX. FlexIO channel 11 or LPUART13 receive. |
| 118 | PTD6 | bidirectional | PORT D | GPIO / FLEXIO_D12 / EMAC_MII_RMII_TX_CLK. FlexIO or Ethernet RMII transmit clock. |
| 119 | PTD7 | bidirectional | PORT D | GPIO / FLEXIO_D13 / EMAC_MII_RMII_TXD0. FlexIO or Ethernet RMII transmit data 0. |
| 120 | PTD8 | bidirectional | PORT D | GPIO / FLEXIO_D14 / EMAC_MII_RMII_TXD1. FlexIO or Ethernet RMII transmit data 1. |
| 121 | PTD9 | bidirectional | PORT D | GPIO / FLEXIO_D15 / EMAC_MII_RMII_TX_EN. FlexIO or Ethernet RMII transmit enable. |
| 122 | PTD10 | bidirectional | PORT D | GPIO / EMAC_MII_RMII_RX_CLK. Ethernet RMII receive clock input (50 MHz reference). |
| 123 | PTD11 | bidirectional | PORT D | GPIO / EMAC_MII_RMII_RXD0. Ethernet RMII receive data 0. |
| 124 | PTD12 | bidirectional | PORT D | GPIO / EMAC_MII_RMII_RXD1. Ethernet RMII receive data 1. |
| 125 | PTD13 | bidirectional | PORT D | GPIO / EMAC_MII_RMII_RX_DV. Ethernet RMII receive data valid / carrier sense. |
| 126 | PTD14 | bidirectional | PORT D | GPIO / EMAC_MII_RMII_RX_ER. Ethernet RMII receive error. |
| 129 | PTD15 | bidirectional | PORT D | GPIO / EMAC_MII_RMII_MDIO. Ethernet management data I/O (MDIO). Requires 1.5kΩ pull-up for MDIO bus. |
| 130 | PTD16 | bidirectional | PORT D | GPIO / EMAC_MII_RMII_MDC. Ethernet management data clock (MDC). Max 2.5 MHz. |
| 131 | PTD17 | bidirectional | PORT D | GPIO / SAI1_BCLK / LPUART14_TX. SAI1 bit clock or LPUART14 transmit. |
| 132 | PTD18 | bidirectional | PORT D | GPIO / SAI1_D0 / LPUART14_RX. SAI1 data or LPUART14 receive. |
| 133 | PTD19 | bidirectional | PORT D | GPIO / SAI1_SYNC / LPUART15_TX. SAI1 frame sync or LPUART15 transmit. |
| 134 | PTD20 | bidirectional | PORT D | GPIO / SAI1_MCLK / LPUART15_RX. SAI1 master clock or LPUART15 receive. |
| 135 | PTD21 | bidirectional | PORT D | GPIO / LPSPI4_SCK. LPSPI4 clock. |
| 136 | PTD22 | bidirectional | PORT D | GPIO / LPSPI4_SIN. LPSPI4 data in. |
| 137 | PTD23 | bidirectional | PORT D | GPIO / LPSPI4_SOUT. LPSPI4 data out. |
| 138 | PTD24 | bidirectional | PORT D | GPIO / LPSPI4_PCS0. LPSPI4 chip select 0. |
| 139 | PTD25 | bidirectional | PORT D | GPIO / LPSPI5_SCK. LPSPI5 clock. |
| 140 | PTD26 | bidirectional | PORT D | GPIO / LPSPI5_SIN. LPSPI5 data in. |
| 141 | PTD27 | bidirectional | PORT D | GPIO / LPSPI5_SOUT. LPSPI5 data out. |
| 142 | PTD28 | bidirectional | PORT D | GPIO / LPSPI5_PCS0. LPSPI5 chip select 0. |
| 143 | PTD29 | bidirectional | PORT D | GPIO / QSPI_A_SCK. QuadSPI clock for external NOR flash. SDR up to 120 MHz. |
| 144 | PTD30 | bidirectional | PORT D | GPIO / QSPI_A_PCS0. QuadSPI chip select for external NOR flash. |
| 145 | PTD31 | bidirectional | PORT D | GPIO / QSPI_A_DATA0. QuadSPI data line 0 (MOSI in SPI mode). |
| 146 | PTE0 | bidirectional | PORT E | GPIO / QSPI_A_DATA1. QuadSPI data line 1 (MISO in SPI mode). |
| 147 | PTE1 | bidirectional | PORT E | GPIO / QSPI_A_DATA2. QuadSPI data line 2 (active in quad/octal modes). |
| 152 | PTE2 | bidirectional | PORT E | GPIO / QSPI_A_DATA3. QuadSPI data line 3 (active in quad/octal modes). |
| 153 | PTE3 | bidirectional | PORT E | GPIO / QSPI_A_DQS. QuadSPI data strobe for DDR mode. Internal DQS dummy pad loopback on S32K344. |
| 154 | PTE4 | bidirectional | PORT E | GPIO / TRACE_D0. Trace data bit 0 for debug trace output. |
| 155 | PTE5 | bidirectional | PORT E | GPIO / TRACE_D1. Trace data bit 1. |
| 156 | PTE6 | bidirectional | PORT E | GPIO / TRACE_D2. Trace data bit 2. |
| 157 | PTE7 | bidirectional | PORT E | GPIO / TRACE_D3. Trace data bit 3. |
| 158 | PTE8 | bidirectional | PORT E | GPIO / TRACE_CLK. Trace clock output for debug trace. |
| 159 | PTE9 | bidirectional | PORT E | GPIO / JTAG_TMS / SWD_DIO. JTAG test mode select or Serial Wire Debug data I/O. |
| 160 | PTE10 | bidirectional | PORT E | GPIO / JTAG_TCK / SWD_CLK. JTAG test clock or Serial Wire Debug clock input. |
| 163 | PTE11 | bidirectional | PORT E | GPIO / JTAG_TDO / SWO. JTAG test data output or Serial Wire Output for trace. |
| 164 | PTE12 | bidirectional | PORT E | GPIO / JTAG_TDI. JTAG test data input. Has internal pull-up. |
| 165 | PTE13 | bidirectional | PORT E | GPIO / JTAG_TRST. JTAG test reset. Has internal pull-up. |
| 166 | PTE14 | bidirectional | PORT E | GPIO / SXOSC_IN. 32.768 kHz slow external oscillator input for RTC. |
| 170 | PTE15 | bidirectional | PORT E | GPIO / SXOSC_OUT. 32.768 kHz slow oscillator output. Crystal connection for RTC. |
| 171 | PTE16 | bidirectional | PORT E | GPIO / TEST. Factory test mode pin — connect to VSS for normal operation. |
| 172 | PTE17 | bidirectional | PORT E | GPIO. General-purpose I/O. |
| 161 | NC | unconnected | SYSTEM | No connect. Leave unconnected. |
| 162 | RESET_B | input | SYSTEM | Active-low system reset input with internal pull-up. Assert low for >1ms to reset the MCU. Has internal glitch filter... |
| 167 | NMI_B | input | SYSTEM | Active-low non-maskable interrupt input with internal pull-up. Directly triggers NMI exception on the Cortex-M7. Use ... |
| 14 | EXTAL | input | CLOCK | Fast external oscillator input (FXOSC). Connect 8–40 MHz crystal between EXTAL and XTAL with appropriate load capacit... |
| 15 | XTAL | output | CLOCK | Fast external oscillator output (FXOSC). Crystal connection — do not load with external circuitry beyond the crystal ... |
| 16 | VREFH | passive | ADC REFERENCE | ADC high reference voltage input. 2.97–5.5V range. Must equal or be close to VDD_HV_A. Decouple with 100nF ceramic ca... |
| 17 | VREFL | passive | ADC REFERENCE | ADC low reference voltage input. Connect to VSS through a short, low-impedance path. Must be within 100mV of VSS for ... |
| 11 | VRC_CTRL | output | REGULATOR | V15 regulator control output. Drives the base of an external NPN ballast transistor for the 1.5V regulator stage. Con... |
| 18 | VDD_HV_A | power_in | POWER SUPPLY | Main I/O and analog supply. 2.97–5.5V. |
| 38 | VDD_HV_B | power_in | POWER SUPPLY | Secondary I/O supply voltage. 2.97–5.5V. |
| 57 | VDD_HV_B | power_in | POWER SUPPLY | Secondary I/O supply voltage. 2.97–5.5V. |
| 77 | VDD_HV_B | power_in | POWER SUPPLY | Secondary I/O supply voltage. 2.97–5.5V. |
| 108 | VDD_HV_A | power_in | POWER SUPPLY | Main I/O and analog supply. 2.97–5.5V. |
| 128 | VDD_HV_A | power_in | POWER SUPPLY | Main I/O and analog supply. 2.97–5.5V. |
| 151 | VDD_HV_A | power_in | POWER SUPPLY | Main I/O and analog supply. 2.97–5.5V. |
| 169 | VDD_HV_A | power_in | POWER SUPPLY | Main I/O and analog supply. 2.97–5.5V. |
| 19 | V25 | power_out | INTERNAL SUPPLY | Flash memory supply (2.5V), internally regulated from VDD_HV_A. Decouple with 220nF ceramic capacitor. Do not connect... |
| 20 | V15 | power_in | INTERNAL SUPPLY | High-current 1.5V logic supply. Decouple with 100nF ceramic. |
| 21 | V11 | power_out | INTERNAL SUPPLY | Core logic supply (1.1V), internally regulated. Decouple with 100nF ceramic. |
| 59 | V11 | power_out | INTERNAL SUPPLY | Core logic supply (1.1V), internally regulated. Decouple with 100nF ceramic. |
| 60 | V15 | power_in | INTERNAL SUPPLY | High-current 1.5V logic supply. Decouple with 100nF ceramic. |
| 105 | V15 | power_in | INTERNAL SUPPLY | High-current 1.5V logic supply. Decouple with 100nF ceramic. |
| 106 | V11 | power_out | INTERNAL SUPPLY | Core logic supply (1.1V), internally regulated. Decouple with 100nF ceramic. |
| 148 | V15 | power_in | INTERNAL SUPPLY | High-current 1.5V logic supply. Decouple with 100nF ceramic. |
| 149 | V11 | power_out | INTERNAL SUPPLY | Core logic supply (1.1V), internally regulated. Decouple with 100nF ceramic. |
| 22 | VSS | power_in | GROUND | Ground. |
| 24 | VSS | power_in | GROUND | Ground. |
| 37 | VSS | power_in | GROUND | Ground. |
| 58 | VSS | power_in | GROUND | Ground. |
| 78 | VSS | power_in | GROUND | Ground. |
| 107 | VSS | power_in | GROUND | Ground. |
| 127 | VSS | power_in | GROUND | Ground. |
| 150 | VSS | power_in | GROUND | Ground. |
| 168 | VSS | power_in | GROUND | Ground. |

## Pin Groups

### PORT A

Port A GPIO pins (PTA0–PTA31). Multiplexed with LPUART0–2, LPI2C0, LPSPI0–1, FlexCAN0–1, and eMIOS0–1 timer channels. Each pin is configured via the SIUL2 IMCR/MSCR registers for pad muxing, drive strength, and pull-up/down.

### PORT B

Port B GPIO pins (PTB0–PTB31). Multiplexed with LPUART3–7, LPI2C1, LPSPI2, FlexCAN2–4, SAI0, FlexIO, and eMIOS0–2 timer channels. Powered by VDD_HV_B supply domain.

### PORT C

Port C GPIO pins (PTC0–PTC31). Host to all ADC0 (channels 8–15) and ADC1 (channels 0–15) analog inputs, plus LPCMP0–2 comparator inputs, LPSPI3, LPUART8–10, FlexCAN5, and eMIOS2 timer channels.

### PORT D

Port D GPIO pins (PTD0–PTD31). Multiplexed with Ethernet RMII (EMAC), SAI1, LPSPI4–5, LPUART11–15, FlexIO, QuadSPI, and additional eMIOS2 channels. Key networking and high-speed peripheral port.

### PORT E

Port E GPIO pins (PTE0–PTE17). Includes QuadSPI data lines, JTAG/SWD debug interface, trace port, and 32.768 kHz slow oscillator (SXOSC) for RTC. Essential for debug access and external NOR flash.

### POWER SUPPLY

Main power supply inputs. VDD_HV_A (2.97–5.5V) powers the primary I/O domain and analog circuits. VDD_HV_B powers the secondary I/O domain. Both require 4.7µF bulk capacitor plus 100nF decoupling per pin.

### INTERNAL SUPPLY

Internal voltage regulator outputs and inputs. V25 (2.5V) powers flash memory. V15 (1.5V) is the high-current logic supply requiring an external NPN ballast transistor. V11 (1.1V) is the internally-regulated core supply. Each requires specific decoupling capacitors.

### GROUND

Ground reference pins. All VSS pins must be connected to a solid, low-impedance ground plane. Critical for analog ADC accuracy, signal integrity, and EMC compliance in automotive environments.

### ADC REFERENCE

ADC voltage reference pins. VREFH sets the ADC full-scale voltage (typically tied to VDD_HV_A). VREFL must be connected to VSS within 100mV. Both require careful decoupling for 12-bit ADC accuracy.

### REGULATOR

Voltage regulator control output. VRC_CTRL drives an external NPN transistor base for the V15 (1.5V) linear regulator. Connect through a 2.2kΩ base resistor. This is the 'last mile regulator' for the 1.5V supply.

### CLOCK

Crystal oscillator interface. EXTAL/XTAL connect to an 8–40 MHz crystal for the Fast External Oscillator (FXOSC). Supports crystal mode and single-ended bypass mode. PLL multiplies this to the 160 MHz core clock.

### SYSTEM

System control pins. RESET_B provides hardware reset with glitch filtering and POR detection. NMI_B triggers non-maskable interrupts for safety-critical events. NC pin must be left unconnected.

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