# Changelog

## 1.0.25 (2026-09-20)
- Heatsink vias written by `heatsinkVias` now carry KiCad's `(property pad_prop_heatsink)` (with `(remove_unused_layers no)`), so KiCad's DRC and fab outputs identify them as thermal vias. 1.0.23 wrote correct plated, tented vias but left them unmarked; found by installing 1.0.24 from the registry and checking its output against the hand-built ToF footprints. A hand-written thermal via can set `"heatsink": true` on its pad.

## 1.0.23 (2026-09-19)
- `heatsinkVias {pad, drill_mm, pitch_mm, ring_mm, tented}` in the create JSON expands to plated `thru_hole` via pads inside the exposed thermal pad, numbered like that pad, on a centred grid that keeps a full annular ring inside it. Only `pad` is required; the defaults are 0.3 mm drill, 0.8 mm pitch, 0.15 mm ring, tented. adom-lbr carries the vias to Altium and Fusion unchanged.
- `create` prints a `HEATSINK VIAS MISSING` hint when the largest SMD pad is a big exposed pad with no plated holes under it, and a via count when they are present.

## 1.0.22 (2026-09-17)
- Silkscreen never lands on copper; pin-1 mark only on polarized parts (Colby Knox). Two-pad parts get two lines outside the copper band instead of a body rectangle through the pads; other parts keep the body outline with every piece within 0.15 mm of a pad cut away. `polarized` in the create JSON controls the pin-1 mark (default: false for two-pad parts, true otherwise).

Earlier history is in the wiki repo commit log.