---
name: adom-fields-verify
description: >-
  Adom Fields fix-and-verify, the readiness report and the inputs assumed: apply fix-plan copper edits (vias, wider traces) to a copy with KiCad refill and DRC and report what moved; a certification-readiness report with Adom Safety and Adom Mechanics; the datasheet fields each assumed input needs. Use when asked to apply and check a fix, "verify the fix", "is it ready for the lab", "readiness report", "what did it assume", "specPatch".
---

Parent skill: **adom-fields**

# Adom Fields: fix and verify, the readiness report, the inputs assumed

## Fix and verify (0.9.3)

`adom-fields verify --board b.kicad_pcb --spec s.json [--step 1,3] [--refill] [--fields <solve>] --out verify` carries out fix-plan steps on a copy of the board, solves the copy, and says what the fix did:
- **Steps it applies (copper edits only):**
  - `add-vias`: a through via, at the board's most common via size, at each point of the action (else `count` of them near `at`). A via is placed only where it lands on the net's own copper on two or more layers and keeps 0.2 mm from other nets. A blocked point moves up to 1 mm (2.5 mm around `at`) to the nearest spot that fits, and `movedMm` says how far.
  - `widen`: the net's segments within 2.5 mm of `at` (on `layer` when given) go to `toMm` (else twice as wide), each only as far as 0.2 mm clearance allows; `short: true` marks one that could not reach the goal.
  - **Each edit sees the earlier ones**, so two neighbouring nets widened in one run keep their clearance to each other.
- **Steps it refuses**, with the reason: `add-part`, `move`, `reroute`, `pour`, `add-copper`, `review`, an impedance width change, and a neck inside a pour (that needs the pour reshaped). Make those in the layout, then `verify` (or `analyze`) the edited file.
- **`--refill`:** KiCad refills the zones and runs DRC (errors only) on both the original and the fixed copy, through `kicad-cli` (service-kicad, else KiCad on the desktop through Adom Bridge). With it:
  - other nets' pours retreat from new copper, as a real refill would;
  - both solves start from refilled boards, so they differ only by the fix;
  - `drc.new` lists the errors the fix introduced.
  - Without `--refill`, other nets' fills count as fixed copper and the copy keeps the fills as saved.
- **Output:**
  - `verify/<board>.kicad_pcb`: the fixed board.
  - `before/` and `after/`: the two solves.
  - `verify.json`: per step, what was applied or why not, and `issueCleared`. Also the issues cleared and new, the metrics that moved (each net's peak density and Joule loss, peak rise still and moving air, each part's rise, ground offset, edge stitching, hot-loop, cable and conducted emissions margins) with `better` true or false, and the DRC result.
- **Reading it:**
  - A peak current density is one cell: widening can move it to a new corner where wide meets narrow. The Joule loss, temperatures and drops are the robust measures.
  - A step can be applied and its issue still be there (a neck at 300 A/mm² against a 60 A/mm² threshold). Read the numbers: they say how far it moved.
  - `--fields <dir>` reuses an existing solve of the same board for the plan and its step numbers.
- **Adopting it:** with `--refill` and no `drc.new`, the fixed board is clean to open in KiCad and save over the original. Without `--refill`, refill and run DRC in KiCad first.

## Certification readiness report (0.9.5)

`adom-fields report --fields <solve> [--safety <adom-safety out>] [--mechanics <adom-mechanics out>] --out readiness.md` writes one readiness report as Markdown, plus the same as `readiness.json`:
- **Areas:** thermal; current and copper; power delivery; signal integrity; EMC and ESD (with the compliance verdicts and the cheapest fix set); electrical safety (from Adom Safety); mechanical reliability (from Adom Mechanics).
- **Each area gets a status** with its key numbers and its first five findings:
  - **blocked:** a high finding, a likely-fail emission test, or a safety distance not met;
  - **needs work:** a medium finding, an at-risk test, no heat sources, or safety nets left on default voltages;
  - **ready:** low findings only;
  - **not checked:** that tool's output was not given, and the report says the command to run.
- **The overall status** is the worst area's.
- **The report also carries:**
  - what it does not cover: measurements, immunity, materials and flammability, DFM;
  - the evidence: tool versions and the board and spec hashes.
- **"Ready" is not "certified".** It means nothing found stands in the way of booking the lab.

## The inputs a solve assumed (0.9.6)

`review.inputs` lists every default or estimate the results lean on, most important first (`matters`: high, medium, low). Each item gives:
- `what` and `used`;
- `from`: default, estimate or missing;
- `part`: its ref and MPN;
- `datasheetField`: the exact datasheet entry that replaces it;
- `specKey`: where the number goes;
- `affects`: what moves, with a sensitivity where one can be computed. For example: "half the edge time costs 6 dB on cable:J2".

The items covered:
- **The converter:** the switch edge and frequency, each capacitor's capacitance at its DC bias and an electrolytic's ESR.
- **Heat:** junction or operating temperature limits, θJC (asked for semiconductors only), and dissipating parts with no watts.
- **Components:** capacitor temperature ratings, and a TDR driver's output resistance and edge.
- **The board:** stackup, laminate Dk, copper weight.
- **The product's world:** ambient, cable lengths, PDN load steps, and a receiver's transistor capacitances.

`specPatch` is the spec fragment to fill in, each value a placeholder naming its source (`<TPS54202DDCR datasheet: switch-node rise time, ns>`). An AI reads the datasheets (the MPN tells it which), fills the patch, and re-runs; an item leaves the list once the spec gives it. `analyze` prints a `Hint: Inputs assumed` line with the high ones.