Adom Fields
Public Made by Adomby adom
Adom Fields: where the current and the heat go on your board.
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781d6ef
name: adom-fields-si description: >- Adom Fields signal-integrity module (--with si): trace and differential-pair impedance from a 2-D field solve, TDR and overshoot in ngspice with the series termination, length matching, via stubs, stackup reference planes, signal capacitance screens. Use when asked about trace impedance, "50 ohm", "90 ohm USB", "differential pair", "TDR", "reflections", "ringing", "series termination", "length matching", "skew".
Parent skill: adom-fields
Adom Fields: signal integrity (--with si)
Turn on si when the board has differential pairs (USB, Ethernet, LVDS, MIPI), clocks or fast buses (SPI, SDIO, QSPI), traces over about 50 mm, or impedance targets.
The reference under each trace (0.10.4)
Each trace segment's reference is found locally, not from whole-layer statistics:
- The rule: on each side, the nearest layer whose ground or supply copper covers 90 % of the segment, sampled at its centre and both edges every 0.25 mm.
- What each
review.impedancerow carries:status;reference.belowandreference.above, each with layer, net,distanceMmand coverage;layersUnder, when the section is unresolved.
- Unresolved sections get no
z0:- mixed reference: a nearer layer covers only part of it;
- no reference: no ground or supply copper under it at all.
- Transitions are separate: points within 0.3 mm of a via, a through-hole or the trace's own pads are not counted, and stretches that are all transition sum to the net's
transitionMm. - Target findings use only referenced sections. A target net or pair with unresolved sections gets a low
impedanceordiff-impedancefinding naming them. - The TDR takes unresolved stretches as 50 Ω and says so (
assumedMm).
Reflections and TDR (0.9.6)
review.reflections checks the nets where edges matter: spec impedance targets, clocks, lengthGroups members, and any net in spec tdr: {net: {driverOhm, riseNs, loadPf, from, to}}.
- The model:
- The path: the net's copper is walked from the driver pad (
from, else the first IC pin) to the receiver (to, else the farthest pad), segment by segment and through vias. - The line: each segment is a lossless line with the cross-section solve's Z0 and delay, and each via adds its pad capacitance (Johnson & Graham).
- What is not modelled: branches off the path are counted, not simulated.
- The path: the net's copper is walked from the driver pad (
- Two ngspice runs:
- TDR: a 50 Ω, 35 ps step gives
tdr.points(ps, Ω), the impedance profile along the path. - In use: the real driver (25 Ω and 1 ns by default; a clock's edge is 7 % of its period) into a 3 pF receiver gives
inUse: overshoot, undershoot, settling time, and the series termination (line Z0 less the driver's resistance).
- TDR: a 50 Ω, 35 ps step gives
- Short nets: a path shorter than a sixth of its edge is
electricallyShortand only says so. - Issues: overshoot over 15 % raises a
reflectionissue, with anadd-partaction for the series resistor at the driver pin. - On the ESC's SWD clock (73 mm, 449 ps of 58 Ω line, a 0.5 ns edge from 20 Ω): 40 % overshoot, fixed by a 38 Ω series resistor. The DShot input (2 ns edge) is electrically short.
impedancesegments'psPerMmis now in ps/mm (it read a million times too high before 0.9.6).
Conducting blocks and signals (0.4.0)
Read docs/heatsinks-and-signals.md in the package before specifying these models. Use measured conductivity/contact resistance for heatsinks; contact is to the board face, not an automatically modeled chip lid. Never add a fictitious heatsink to make a gate pass. Inspect both air conditions and mesh sensitivity.
For signal screening, provide signals.capacitance or signals.differentialPairs, explicit consistent stackupMm, and justified epsilonR. Inspect Signals with adom-fields ui --port 8874 view --quantity signals. Unsupported geometry must stay unsupported; do not replace null estimates with guessed numbers. This is outer-layer microstrip and adjacent-layer overlap screening, not high-frequency signoff. The summary records assumptions and primary references.
Also in this area
- Trace impedance (0.9.0,
review.impedance): a 2-D Laplace field solve of every signal net's cross-section on its own layer (microstrip or stripline, solder mask unlessrf.noSolderMask).- It gives Z0, εeff, ps/mm, pF/m and nH/m, plus Zodd, Zeven and Zdiff for pairs found by name (_P/_N, +/-, DP/DM).
- Targets come from spec
impedance{net: Ω, "P/N": Ω differential} or by protocol (USB 90, PCIe 85, Ethernet/LVDS/HDMI/MIPI 100). - It is validated within about 2 % of Hammerstad-Jensen and Cohn.
---
name: adom-fields-si
description: >-
Adom Fields signal-integrity module (--with si): trace and differential-pair impedance from a 2-D field solve, TDR and overshoot in ngspice with the series termination, length matching, via stubs, stackup reference planes, signal capacitance screens. Use when asked about trace impedance, "50 ohm", "90 ohm USB", "differential pair", "TDR", "reflections", "ringing", "series termination", "length matching", "skew".
---
Parent skill: **adom-fields**
# Adom Fields: signal integrity (`--with si`)
Turn on `si` when the board has differential pairs (USB, Ethernet, LVDS, MIPI), clocks or fast buses (SPI, SDIO, QSPI), traces over about 50 mm, or impedance targets.
## The reference under each trace (0.10.4)
Each trace segment's reference is found locally, not from whole-layer statistics:
- **The rule:** on each side, the nearest layer whose ground or supply copper covers 90 % of the segment, sampled at its centre and both edges every 0.25 mm.
- **What each `review.impedance` row carries:**
- `status`;
- `reference.below` and `reference.above`, each with layer, net, `distanceMm` and coverage;
- `layersUnder`, when the section is unresolved.
- **Unresolved sections get no `z0`:**
- **mixed reference:** a nearer layer covers only part of it;
- **no reference:** no ground or supply copper under it at all.
- **Transitions are separate:** points within 0.3 mm of a via, a through-hole or the trace's own pads are not counted, and stretches that are all transition sum to the net's `transitionMm`.
- **Target findings** use only referenced sections. A target net or pair with unresolved sections gets a low `impedance` or `diff-impedance` finding naming them.
- **The TDR** takes unresolved stretches as 50 Ω and says so (`assumedMm`).
## Reflections and TDR (0.9.6)
`review.reflections` checks the nets where edges matter: spec `impedance` targets, `clocks`, `lengthGroups` members, and any net in spec `tdr: {net: {driverOhm, riseNs, loadPf, from, to}}`.
- **The model:**
- **The path:** the net's copper is walked from the driver pad (`from`, else the first IC pin) to the receiver (`to`, else the farthest pad), segment by segment and through vias.
- **The line:** each segment is a lossless line with the cross-section solve's Z0 and delay, and each via adds its pad capacitance (Johnson & Graham).
- **What is not modelled:** branches off the path are counted, not simulated.
- **Two ngspice runs:**
- **TDR:** a 50 Ω, 35 ps step gives `tdr.points` (ps, Ω), the impedance profile along the path.
- **In use:** the real driver (25 Ω and 1 ns by default; a clock's edge is 7 % of its period) into a 3 pF receiver gives `inUse`: overshoot, undershoot, settling time, and the series termination (line Z0 less the driver's resistance).
- **Short nets:** a path shorter than a sixth of its edge is `electricallyShort` and only says so.
- **Issues:** overshoot over 15 % raises a `reflection` issue, with an `add-part` action for the series resistor at the driver pin.
- **On the ESC's SWD clock** (73 mm, 449 ps of 58 Ω line, a 0.5 ns edge from 20 Ω): 40 % overshoot, fixed by a 38 Ω series resistor. The DShot input (2 ns edge) is electrically short.
- `impedance` segments' `psPerMm` is now in ps/mm (it read a million times too high before 0.9.6).
## Conducting blocks and signals (0.4.0)
Read `docs/heatsinks-and-signals.md` in the package before specifying these models. Use measured conductivity/contact resistance for `heatsinks`; contact is to the board face, not an automatically modeled chip lid. Never add a fictitious heatsink to make a gate pass. Inspect both air conditions and mesh sensitivity.
For signal screening, provide `signals.capacitance` or `signals.differentialPairs`, explicit consistent `stackupMm`, and justified epsilonR. Inspect Signals with `adom-fields ui --port 8874 view --quantity signals`. Unsupported geometry must stay unsupported; do not replace null estimates with guessed numbers. This is outer-layer microstrip and adjacent-layer overlap screening, not high-frequency signoff. The summary records assumptions and primary references.
## Also in this area
- **Trace impedance** (0.9.0, `review.impedance`): a 2-D Laplace field solve of every signal net's cross-section on its own layer (microstrip or stripline, solder mask unless `rf.noSolderMask`).
- It gives Z0, εeff, ps/mm, pF/m and nH/m, plus Zodd, Zeven and Zdiff for pairs found by name (_P/_N, +/-, DP/DM).
- Targets come from spec `impedance` {net: Ω, "P/N": Ω differential} or by protocol (USB 90, PCIe 85, Ethernet/LVDS/HDMI/MIPI 100).
- It is validated within about 2 % of Hammerstad-Jensen and Cohn.