Adom Fields
Public Made by Adomby adom
Adom Fields: where the current and the heat go on your board.
main
f01bf13
name: adom-fields-review description: >- Every Adom Fields finding kind, which module produces it, grouped findings, the review blocks and the fix plan, budgets and the IR-drop probe. Use when reading adom-fields issues or fixPlan, "what does this finding mean", "current-neck", "decoupling-far", "group action", "fixPlan", "review block", "ir drop probe".
Parent skill: adom-fields
Adom Fields: the findings, the review and the fix plan
Every finding kind, which module it comes from (core always runs; the rest need --with <module>), and the review blocks behind them.
Copper pieces and KiCad 8 boards (0.10.3)
- Separate pieces stay separate. Same-net copper the board keeps apart (two fills closer than a solve cell, joined only through other layers) is no longer joined by the grid. Each net's copper is split into the pieces that really touch, and every spot where two pieces came closer than a cell is in
nets[].piecesKeptApart(layer and position). A peak near such a spot is real; for the exact copper there, re-run at--pitch 0.1. - KiCad 8 files work. Tracks and vias written
(net 41)resolve through the board's net table. A number the table does not list stops the run with the count; open and save the board in KiCad to fix it.
Finding kinds by module
core always runs; the others need --with <module> (or the spec keys listed in SKILL.md). Kinds not listed are core: current-neck, current-barrel, ampacity, ir-drop, pour-fragmented, tab-rise, thermal-vias, junction-temperature, capacitor-temperature, electro-thermal, solid-uncoupled, ground-offset, ground-island, decoupling-far, decoupling-missing, hot-loop, inductor-ripple, output-ripple, solve-unconverged, load-unsolved.
| Module | Kinds |
|---|---|
emc |
emissions, cable-emissions, conducted-emissions, stitching-gap, ground-loop-risk, no-reference, clock-outer-layer, clock-near-connector, edge-signal, input-filter-cutoff |
esd |
esd-unprotected, io-unfiltered |
pdn |
pdn-impedance, input-filter-stability, hot-plug-overshoot, regulator |
si |
impedance, diff-impedance, reflection, length-skew, via-stub, stackup-adjacent-signals, stackup-far-reference, plane |
noise |
cavity-resonance, crosstalk, tone-in-band |
rf |
lo-leak, stage-isolation, lo-emission, stage-feed-unbypassed, circuit-path, antenna-ground-loop |
Grouping: three or more low findings of one kind become one finding (action.type: group, every item with its own action in action.items); per-via current-barrel warnings become one per net; ampacity on a net that already has a current-neck folds into it. verify carries out a group's items one by one. With spec external: ["J1", ...], esd-unprotected and io-unfiltered cover only those connectors.
For the AI that called the solve: the review and the fix plan (0.7.6)
analyze reviews the design as well as solving it, and says what to change, without anyone looking at the app:
fields.jsonissues: every finding withseverity,kind,what,at(board mm),net,reference, a plainfix, and anactionto carry out:move(ref,toPins,targetMm2),add-vias(net,pointsorat,pitchMm),widen(net,at),pour(net,layer,under,at),add-copper,add-part,review. Kinds:current-neck,tab-rise,thermal-vias(the solve's own), and from the reviewhot-loop,emissions,no-reference,ground-offset,ground-island,stitching-gap,ground-loop-risk,ir-drop(overdropPctof the rail, or over the net's ownloads.<net>.maxDropMv),pour-fragmented(a poured net's fill on one layer broke into pieces: the nearest gap, the pad in it, and amove(reference,orRotateDeg,byMm) orrerouteaction;fields.jsonfragmentslists every pour's pieces per layer),inductor-ripple,output-ripple,decoupling-far,decoupling-missing(each chip power pin's nearest small capacitor to any ground the chip has a pin on, or to the review's ground, recorded asreturninreview.decoupling: over 3 mm moves it, none adds a 100 nF),solid-uncoupled(a solid body the solve left out:boardContactM2kWset but no face on the copper is high; no heat and no path to the board, so 0 W, is medium),cavity-resonance,crosstalk,esd-unprotected(a connector pin with no diode to any ground: add a TVS within 3 mm if it faces the outside).fields.jsonfixPlan: the actions, worst first and concrete edits before reviews, numbered for the caller to work down.analyzeprints the first five as aHint: Fix planline and the review as aHint: Reviewline.fields.jsonreview: the numbers behind them:converter(duty, ripple, hot loops per input capacitor and the best possible, the emissions margin),reference(each net's copper with no ground under it),ground(offset, connectors to the outside, islands, the stitching fence and its gaps),rails(IR drop per rail),decoupling(pin, cap, distance, loop),esd(each connector pin and what protects it).- IR-drop probe:
adom-fields probe --fields <dir> --from J1.1 --to U1.3(or--to <net>for its farthest point,--jsonfor the record) reads the drop between two pads from the solve, no re-solve;adom-fields ui probe --from J1.1 --to U1.3shows it in the running app's river view with a toast. - Budgets in the spec:
groundOffsetMv(10),dropPct(1 % of the rail),loads.<net>.maxDropMv(none;review.dropslists every loaded net's drop and its two ends),emcFmaxHz(1 GHz, for the stitching pitch),switching.<net>.riseNs(8).
After applying a step, run analyze again: the issue goes away or says how far it still is. In the app, clicking an issue opens the view that shows it (EMC, Ground, River, Cycle).
Hot parts read at their tab (0.9.8)
A hot part with a tab net is read at its tab: the pad named in hot.<ref>.tabPad (the exposed pad's number, e.g. "29"), else the largest tab-net pad, so an exposed pad wins over corner pins that share its net. vias counts the tab net's vias near every tab-net pad, including a footprint's own thermal-via holes. The watts are still spread over all tab-net pads by area.
Also in this area
- Board checks (0.9.0,
review.checks), on the solved fields where one exists:ampacity: each loaded net's narrowest neck against IPC-2221's 10 °C rating, beside the solved rise there.junctions/junction-temperature: ambient (specambientC, 25) + the solved rise (+hot.<ref>.thetaJcKPerW·W) againsthot.<ref>.tjMaxC(125).capacitors/capacitor-temperature: each capacitor's solved temperature against its type's rating (a °C rating or dielectric in the value, else the vendor's code in the footprint's MPN field: Samsung CL, Murata GRM/GCM, TDK, Yageo, KEMET, Walsin; each entry givesdielectricandratingFrom, andratingAssumedwhen neither says; electrolytic life by the 10 °C rule; ceramics with only an assumed rating grouped into one finding).emcRules:clock-outer-layer,clock-near-connector,edge-signal,io-unfiltered,input-filter-cutoff(a converter's input LC against fsw/10).stackup: which layers are planes, plusstackup-far-reference,stackup-adjacent-signalsand plane-pair pF/cm².viaStubs/via-stub: the quarter-wave resonance of each signal via's unused barrel against its clock.lengthGroups/length-skew: speclengthGroups{name: {nets, maxSkewPs | maxSkewMm | protocol: usb2|usb3|pcie|ethernet|ddr|hdmi|mipi}}.
---
name: adom-fields-review
description: >-
Every Adom Fields finding kind, which module produces it, grouped findings, the review blocks and the fix plan, budgets and the IR-drop probe. Use when reading adom-fields issues or fixPlan, "what does this finding mean", "current-neck", "decoupling-far", "group action", "fixPlan", "review block", "ir drop probe".
---
Parent skill: **adom-fields**
# Adom Fields: the findings, the review and the fix plan
Every finding kind, which module it comes from (`core` always runs; the rest need `--with <module>`), and the review blocks behind them.
## Copper pieces and KiCad 8 boards (0.10.3)
- **Separate pieces stay separate.** Same-net copper the board keeps apart (two fills closer than a solve cell, joined only through other layers) is no longer joined by the grid. Each net's copper is split into the pieces that really touch, and every spot where two pieces came closer than a cell is in `nets[].piecesKeptApart` (layer and position). A peak near such a spot is real; for the exact copper there, re-run at `--pitch 0.1`.
- **KiCad 8 files work.** Tracks and vias written `(net 41)` resolve through the board's net table. A number the table does not list stops the run with the count; open and save the board in KiCad to fix it.
## Finding kinds by module
`core` always runs; the others need `--with <module>` (or the spec keys listed in SKILL.md). Kinds not listed are core: `current-neck`, `current-barrel`, `ampacity`, `ir-drop`, `pour-fragmented`, `tab-rise`, `thermal-vias`, `junction-temperature`, `capacitor-temperature`, `electro-thermal`, `solid-uncoupled`, `ground-offset`, `ground-island`, `decoupling-far`, `decoupling-missing`, `hot-loop`, `inductor-ripple`, `output-ripple`, `solve-unconverged`, `load-unsolved`.
| Module | Kinds |
|---|---|
| `emc` | `emissions`, `cable-emissions`, `conducted-emissions`, `stitching-gap`, `ground-loop-risk`, `no-reference`, `clock-outer-layer`, `clock-near-connector`, `edge-signal`, `input-filter-cutoff` |
| `esd` | `esd-unprotected`, `io-unfiltered` |
| `pdn` | `pdn-impedance`, `input-filter-stability`, `hot-plug-overshoot`, `regulator` |
| `si` | `impedance`, `diff-impedance`, `reflection`, `length-skew`, `via-stub`, `stackup-adjacent-signals`, `stackup-far-reference`, `plane` |
| `noise` | `cavity-resonance`, `crosstalk`, `tone-in-band` |
| `rf` | `lo-leak`, `stage-isolation`, `lo-emission`, `stage-feed-unbypassed`, `circuit-path`, `antenna-ground-loop` |
Grouping: three or more low findings of one kind become one finding (`action.type: group`, every item with its own action in `action.items`); per-via `current-barrel` warnings become one per net; `ampacity` on a net that already has a `current-neck` folds into it. `verify` carries out a group's items one by one. With spec `external: ["J1", ...]`, `esd-unprotected` and `io-unfiltered` cover only those connectors.
## For the AI that called the solve: the review and the fix plan (0.7.6)
`analyze` reviews the design as well as solving it, and says what to change, without anyone looking at the app:
- **`fields.json` `issues`**: every finding with `severity`, `kind`, `what`, `at` (board mm), `net`, `reference`, a plain `fix`, and an **`action`** to carry out: `move` (`ref`, `toPins`, `targetMm2`), `add-vias` (`net`, `points` or `at`, `pitchMm`), `widen` (`net`, `at`), `pour` (`net`, `layer`, `under`, `at`), `add-copper`, `add-part`, `review`. Kinds: `current-neck`, `tab-rise`, `thermal-vias` (the solve's own), and from the review `hot-loop`, `emissions`, `no-reference`, `ground-offset`, `ground-island`, `stitching-gap`, `ground-loop-risk`, `ir-drop` (over `dropPct` of the rail, or over the net's own `loads.<net>.maxDropMv`), `pour-fragmented` (a poured net's fill on one layer broke into pieces: the nearest gap, the pad in it, and a `move` (`reference`, `orRotateDeg`, `byMm`) or `reroute` action; `fields.json` `fragments` lists every pour's pieces per layer), `inductor-ripple`, `output-ripple`, `decoupling-far`, `decoupling-missing` (each chip power pin's nearest small capacitor to any ground the chip has a pin on, or to the review's ground, recorded as `return` in `review.decoupling`: over 3 mm moves it, none adds a 100 nF), `solid-uncoupled` (a solid body the solve left out: `boardContactM2kW` set but no face on the copper is high; no heat and no path to the board, so 0 W, is medium), `cavity-resonance`, `crosstalk`, `esd-unprotected` (a connector pin with no diode to any ground: add a TVS within 3 mm if it faces the outside).
- **`fields.json` `fixPlan`**: the actions, worst first and concrete edits before reviews, numbered for the caller to work down. `analyze` prints the first five as a `Hint: Fix plan` line and the review as a `Hint: Review` line.
- **`fields.json` `review`**: the numbers behind them: `converter` (duty, ripple, hot loops per input capacitor and the best possible, the emissions margin), `reference` (each net's copper with no ground under it), `ground` (offset, connectors to the outside, islands, the stitching fence and its gaps), `rails` (IR drop per rail), `decoupling` (pin, cap, distance, loop), `esd` (each connector pin and what protects it).
- **IR-drop probe**: `adom-fields probe --fields <dir> --from J1.1 --to U1.3` (or `--to <net>` for its farthest point, `--json` for the record) reads the drop between two pads from the solve, no re-solve; `adom-fields ui probe --from J1.1 --to U1.3` shows it in the running app's river view with a toast.
- Budgets in the spec: `groundOffsetMv` (10), `dropPct` (1 % of the rail), `loads.<net>.maxDropMv` (none; `review.drops` lists every loaded net's drop and its two ends), `emcFmaxHz` (1 GHz, for the stitching pitch), `switching.<net>.riseNs` (8).
After applying a step, run `analyze` again: the issue goes away or says how far it still is. In the app, clicking an issue opens the view that shows it (EMC, Ground, River, Cycle).
## Hot parts read at their tab (0.9.8)
A hot part with a tab net is read at its tab: the pad named in `hot.<ref>.tabPad` (the exposed pad's number, e.g. `"29"`), else the largest tab-net pad, so an exposed pad wins over corner pins that share its net. `vias` counts the tab net's vias near every tab-net pad, including a footprint's own thermal-via holes. The watts are still spread over all tab-net pads by area.
## Also in this area
- **Board checks** (0.9.0, `review.checks`), on the solved fields where one exists:
- `ampacity`: each loaded net's narrowest neck against IPC-2221's 10 °C rating, beside the solved rise there.
- `junctions` / `junction-temperature`: ambient (spec `ambientC`, 25) + the solved rise (+ `hot.<ref>.thetaJcKPerW`·W) against `hot.<ref>.tjMaxC` (125).
- `capacitors` / `capacitor-temperature`: each capacitor's solved temperature against its type's rating (a °C rating or dielectric in the value, else the vendor's code in the footprint's MPN field: Samsung CL, Murata GRM/GCM, TDK, Yageo, KEMET, Walsin; each entry gives `dielectric` and `ratingFrom`, and `ratingAssumed` when neither says; electrolytic life by the 10 °C rule; ceramics with only an assumed rating grouped into one finding).
- `emcRules`: `clock-outer-layer`, `clock-near-connector`, `edge-signal`, `io-unfiltered`, `input-filter-cutoff` (a converter's input LC against fsw/10).
- `stackup`: which layers are planes, plus `stackup-far-reference`, `stackup-adjacent-signals` and plane-pair pF/cm².
- `viaStubs` / `via-stub`: the quarter-wave resonance of each signal via's unused barrel against its clock.
- `lengthGroups` / `length-skew`: spec `lengthGroups` {name: {nets, maxSkewPs | maxSkewMm | protocol: usb2|usb3|pcie|ethernet|ddr|hdmi|mipi}}.