# adom-fields 0.9.0

The first release of the PCB-analysis roadmap: the checks other PCB review tools make by rule of thumb, done here on the solved copper wherever a field exists, plus three new solvers.

- **Common-mode cable emissions (`review.cableEmissions`, `cable-emissions`).** This is the usual reason a board fails the chamber.
  - **The model:** the switching loop's harmonic current flows across the ground copper's inductance between the loop and each connector's ground pin. That inductance is μ0·h × the squares of ground, taken from the solved DC ground field. The voltage it raises drives the connector's cable (spec `cables`, 1 m by default) as a monopole, checked against the chosen limit at 3 m.
  - **Status:** an upper bound with no ferrite.
  - **Example:** on the TPS54202 buck with 1 m cables, it lands 2–7 dB over FCC class B at 63 MHz, where the loop's own differential-mode estimate is 55 dB under.
- **Trace impedance by a 2-D field solve (`review.impedance`, `impedance`, `diff-impedance`).**
  - **The solve:** every signal net's cross-section on its own layer, microstrip or stripline, with solder mask, on a non-uniform grid. It is solved in the dielectric and in air.
  - **Results:** Z0, εeff, ps/mm, pF/m and nH/m; Zodd, Zeven and Zdiff for pairs found by name.
  - **Targets:** from spec `impedance`, or by protocol (USB 90 Ω, PCIe 85 Ω, Ethernet/LVDS/HDMI/MIPI 100 Ω differential).
  - **Accuracy:** within 1 % of Hammerstad-Jensen (microstrip) and Wadell (stripline). Delays may read about 3 % fast.
- **Emission limit sets.** Spec `emcLimit` picks the set the issues use: `fcc-b` (default), `fcc-a`, `cispr32-b`, `cispr32-a`, or a custom line from spec `emcLimits` (CISPR 25, MIL-STD-461 RE102, a customer's). Every emission estimate also reports its margin against every set.
- **Board checks (`review.checks`):**
  - **Ampacity:** each loaded net's narrowest neck against IPC-2221's 10 °C rating, beside the solved rise there.
  - **Junction temperature:** ambient + the solved rise (+ θjc × W) against each hot part's `tjMaxC`.
  - **Capacitor temperature:** against each part's rating read from its value or part number. Electrolytic life uses the 10 °C rule. Ceramics with an assumed rating are grouped into one finding.
  - **EMC layout rules:** clocks on outer layers or near connectors, signals along the board edge, unfiltered connector I/O, and a converter's input filter against fsw/10.
  - **Stackup:** detects which layers are planes; flags signal layers far from a plane and adjacent signal layers; gives plane-pair capacitance.
  - **Via stubs:** quarter-wave resonance against the net's clock.
  - **Length groups:** delay skew against `maxSkewPs`, `maxSkewMm` or a protocol limit.
- **The app opens the right view for each new finding** (current, temperature, EMC, signals or noise).