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Adom Fields
Public Made by Adomby adom
Adom Fields: where the current and the heat go on your board.
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John Lauer
adom-fields 0.7.17: the open PRs merged onto 0.7.16. Plated pad barrels and drill voids with wall coupling (5, 9), expl…
df40420
adom-fields 0.7.17
The open pull requests, reviewed and merged onto 0.7.16 (credit: the electronic-load thread's PRs 5, 6, 8, 9, 10, 11 and 12).
- Plated through-hole pads join the layers like vias, electrically and thermally, circular or slotted (PR 5). A connector's plated pad no longer leaves its bottom ground floating.
- Drill holes are voids, and each barrel couples around its plated wall rather than at one centre cell (PR 9); a barrel the mesh cannot resolve falls back to its nearest copper cells, so a small via never splits a net at a coarse pitch (issue 11). Each plated hole's current is reported.
- Explicit pin currents per loaded net, with physical-land selectors for repeated pin numbers (PR 6, 10). A net the spec names that cannot be solved fails the run rather than publishing a partial report.
- The true peak current density is reported before the display clip (PR 8): a narrow neck over the limit no longer passes.
- Package cooling: a hot part's junction, case and sink as nodes with supplied resistances, power split and energy balance (PR 11).
thermal3d: a separate 3D solid conduction solve for off-board packages and finned sinks, with a temperature GLB (PR 12).- Ported, not merged as written: PR 5's two-or-four-layer stack check (0.7.16 already reads two, four or six layers) and its refusal to publish an unconverged net (0.7.16 reports it as an issue instead, as issue 9 asked).
# adom-fields 0.7.17
The open pull requests, reviewed and merged onto 0.7.16 (credit: the electronic-load thread's PRs 5, 6, 8, 9, 10, 11 and 12).
- **Plated through-hole pads join the layers** like vias, electrically and thermally, circular or slotted (PR 5). A connector's plated pad no longer leaves its bottom ground floating.
- **Drill holes are voids**, and each barrel couples around its plated wall rather than at one centre cell (PR 9); a barrel the mesh cannot resolve falls back to its nearest copper cells, so a small via never splits a net at a coarse pitch (issue 11). Each plated hole's current is reported.
- **Explicit pin currents** per loaded net, with physical-land selectors for repeated pin numbers (PR 6, 10). A net the spec names that cannot be solved fails the run rather than publishing a partial report.
- **The true peak current density** is reported before the display clip (PR 8): a narrow neck over the limit no longer passes.
- **Package cooling**: a hot part's junction, case and sink as nodes with supplied resistances, power split and energy balance (PR 11).
- **`thermal3d`**: a separate 3D solid conduction solve for off-board packages and finned sinks, with a temperature GLB (PR 12).
- Ported, not merged as written: PR 5's two-or-four-layer stack check (0.7.16 already reads two, four or six layers) and its refusal to publish an unconverged net (0.7.16 reports it as an issue instead, as issue 9 asked).