app
Adom Fields
Public Made by Adomby adom
Adom Fields: where the current and the heat go on your board.
main
John Lauer
adom-fields 0.7.16: the community's issues. #10 plated pads only on real copper, stackup from the board; #11 six-layer…
ee2efa2
adom-fields 0.7.16
Built from the community's issues: #10 (senthilkumaranms), #9 (Noah's RF review of the AM/FM receiver), #11 and #8.
The copper stack (#10, #11, #8)
- A plated pad goes only onto copper the board has: a two-layer board solves on F.Cu and B.Cu, never on phantom inner layers.
- Two-, four- and six-layer boards. The stack is checked (F.Cu, In1.Cu .. In.Cu, B.Cu, contiguous); more than six layers is refused by name.
- The dielectric comes from the spec (one value per real gap; three values on a two-layer board are summed, the old form), else the board's own saved stackup, else its thickness. εr per gap comes from the stackup (spec
epsilonRotherwise). fields.json reportscopperLayers,dielectricMm(the real gaps) andstackupFrom. - The solver refines its answer until the true residual meets the target (CG's own residual drifts on badly conditioned nets), and copper pieces with terminals but no path to the rest are referenced on their own instead of stalling the solve. A net that still does not converge is a
solve-unconvergedissue and its numbers are kept out of the review.
Heat (#8)
hot.<part>.tabNetis optional: a leaded part with no exposed tab puts its watts through all its leads, by pad area.- With no heat sources modelled, fields.json and the hints say the temperature is only the copper's I²R loss, not a thermal pass for any part.
RF and receivers (#9)
- Plane cavities on every adjacent layer pair in both directions, each with its own gap and εr (the inner planes were never examined before).
clockstake a frequency or{hz | minHz + maxHz, harmonics, amplitudeV}: a tuned LO sweeps. A crystal or an LC oscillator counts to its 5th harmonic as a strong tone.- Frequency plan (
bands:{name: {minHz, maxHz, ifHz, lowSideLo}}): every harmonic of every clock, weak ones included, checked against each receive band and its image:tone-in-band. - Crosstalk in the victim's real impedance: an oscillator is a sine at its amplitude and frequency, V = A·ωCm / |jω(Cm + Cg) + G|, with Cg including the capacitors on the victim net and G its resistors to ground or a rail; the victim's own plane gap; side coupling out to 3 mm with plane shielding; overlap on every adjacent layer pair. Per-net budgets (
victimBudgetsMv) and µV reporting. - Circuit paths (
sensitiveNets): each path through the parts from an oscillator to a sensitive net (an antenna, an IF input) is reported, for a simulation. - Return path for every net: over ground, over a supply plane (its return rides the bypass capacitors) or over nothing; switching, clock, signal-pair and sensitive nets medium.
- Antenna ground loop: a cable connector's ground on the board near the antenna connector, with the common-mode fix.
- Stage feeds: each transistor stage's supply resistor and its bypass capacitors (corner frequency, self-resonance); a feed with no bypass is an issue.
- Stitching counts plated ground pads and holes as fence posts, and sizes the fence from the board's own tones.
- An RF input's ESD advice carries a capacitance budget; per-layer lengths on differential pairs show why a pair is not one.
- Ground is solved even when the spec lists only the supplies (the largest supply load as the return current, stated);
+3.3VAreads as 3.3 V. - The Noise view uses the solve's budgets, µV units and converter-free wording; each view's tags and panel show only in that view, even from a background tab.
# adom-fields 0.7.16
Built from the community's issues: #10 (senthilkumaranms), #9 (Noah's RF review of the AM/FM receiver), #11 and #8.
**The copper stack (#10, #11, #8)**
- A plated pad goes only onto copper the board has: a two-layer board solves on F.Cu and B.Cu, never on phantom inner layers.
- Two-, four- and six-layer boards. The stack is checked (F.Cu, In1.Cu .. In<n>.Cu, B.Cu, contiguous); more than six layers is refused by name.
- The dielectric comes from the spec (one value per real gap; three values on a two-layer board are summed, the old form), else the board's own saved stackup, else its thickness. εr per gap comes from the stackup (spec `epsilonR` otherwise). fields.json reports `copperLayers`, `dielectricMm` (the real gaps) and `stackupFrom`.
- The solver refines its answer until the true residual meets the target (CG's own residual drifts on badly conditioned nets), and copper pieces with terminals but no path to the rest are referenced on their own instead of stalling the solve. A net that still does not converge is a `solve-unconverged` issue and its numbers are kept out of the review.
**Heat (#8)**
- `hot.<part>.tabNet` is optional: a leaded part with no exposed tab puts its watts through all its leads, by pad area.
- With no heat sources modelled, fields.json and the hints say the temperature is only the copper's I²R loss, not a thermal pass for any part.
**RF and receivers (#9)**
- Plane cavities on every adjacent layer pair in both directions, each with its own gap and εr (the inner planes were never examined before).
- `clocks` take a frequency or `{hz | minHz + maxHz, harmonics, amplitudeV}`: a tuned LO sweeps. A crystal or an LC oscillator counts to its 5th harmonic as a strong tone.
- **Frequency plan** (`bands`: `{name: {minHz, maxHz, ifHz, lowSideLo}}`): every harmonic of every clock, weak ones included, checked against each receive band and its image: `tone-in-band`.
- **Crosstalk** in the victim's real impedance: an oscillator is a sine at its amplitude and frequency, V = A·ωCm / |jω(Cm + Cg) + G|, with Cg including the capacitors on the victim net and G its resistors to ground or a rail; the victim's own plane gap; side coupling out to 3 mm with plane shielding; overlap on every adjacent layer pair. Per-net budgets (`victimBudgetsMv`) and µV reporting.
- **Circuit paths** (`sensitiveNets`): each path through the parts from an oscillator to a sensitive net (an antenna, an IF input) is reported, for a simulation.
- **Return path** for every net: over ground, over a supply plane (its return rides the bypass capacitors) or over nothing; switching, clock, signal-pair and sensitive nets medium.
- **Antenna ground loop**: a cable connector's ground on the board near the antenna connector, with the common-mode fix.
- **Stage feeds**: each transistor stage's supply resistor and its bypass capacitors (corner frequency, self-resonance); a feed with no bypass is an issue.
- Stitching counts plated ground pads and holes as fence posts, and sizes the fence from the board's own tones.
- An RF input's ESD advice carries a capacitance budget; per-layer lengths on differential pairs show why a pair is not one.
- Ground is solved even when the spec lists only the supplies (the largest supply load as the return current, stated); `+3.3VA` reads as 3.3 V.
- The Noise view uses the solve's budgets, µV units and converter-free wording; each view's tags and panel show only in that view, even from a background tab.