# adom-fields 0.10.7

Issues 25 and 26, plus a `verify` fix found while testing them.

- **The board's ground (issue 25).** Any net whose name ends in GND counted as ground, and the first one in alphabetical order won. On a board with GND and BRIDGE_GND (a motor bridge's return, joined to GND only through a shunt), BRIDGE_GND became the ground, and the ground offset, stitching, decoupling and ESD checks were measured against it. On a board with AGND and PGND, the small AGND won.
  - The ground is now spec `ground` when given, else the net named GND, else the ground-named net the most pads are on.
  - `review.ground` records `groundFrom` and `groundNets`, so a wrong pick shows. A spec `ground` that isn't a net on the board is refused.
  - The same pick is used for the ground's own current solve and the noise review. The hot loop's cable emissions use the converter's power ground.
  - A protector diode or a stage-feed bypass capacitor to any ground now counts. Before, only one to the picked ground did, which gave false `esd-unprotected` and `stage-feed-unbypassed` findings.
  - `--with pdn` judged a rail only on capacitors to the picked ground, so a rail decoupled to PGND on a board whose ground was another net got no verdict or a wrong one. Each rail now uses the ground most of its capacitors go to, recorded as `return`. `capsToOtherGrounds` lists any it leaves out.
- **Coincident lands (issue 26).** TI's DGN0008B footprint has pad 9 eight times, two of them at the centre: a 2 x 3 mm land and a 1.6 x 2.94 mm one. No `at` could name one of them, so the terminal was refused.
  - Lands of one pad number at one centre on one net are now one piece of copper: `at` names it, and the largest land stands for it.
  - Naming it twice is still refused, and so is coincident copper on two nets.
  - With no `at` the pin is still ambiguous, and the error now says to give one.
- **`verify` kept a stitching via's centre, not its copper, 0.5 mm from the edge.** Applying the fix plan's stitching vias on the 12 V buck put one 0.1 mm from the edge, and KiCad's DRC failed it. The via's copper now keeps 0.5 mm. The fix plan's suggested points sit the via's radius plus 0.5 mm in, where they used to sit 0.6 mm in. Where no spot within reach keeps that and lands on the ground on both layers, `verify` skips the step and says so.

**What moves on your boards:** only boards with more than one ground net, or a ground not named GND. On single-ground boards (12 V buck, CM5 Minima, StickHub, tinytapeout demo), every finding with every module is unchanged.

**Checked:**

- Issue 25, on a test board built to the issue (GND, and BRIDGE_GND carrying 10 A through a shunt):
  - The ground is now GND, not BRIDGE_GND, and the false `esd-unprotected` on the protected USB line is gone.
  - A unit test covers the other side of it: a capacitor that only reaches BRIDGE_GND no longer counts as decoupling a chip that is only on GND.
  - With spec `ground: "BRIDGE_GND"` the old pick comes back. A spec ground that isn't on the board is refused.
- BQ25792 charger (Fusion `.brd`, AGND with 2 pads and PGND with 28):
  - The ground moves from AGND to PGND, and the stitching findings follow it.
  - PDN now lists all 6 rails, instead of silently skipping them. Each still needs spec `sources` for a verdict.
- PDN test board, ground GND, +3V3 decoupled to PGND: judged on PGND with C1 and C2. 0.10.6 judged it on the one capacitor to GND.
- Issue 26: the centre lands with `at` now solve, as does a mixed centre and via-pad split. Naming the centre twice, and leaving out `at`, are refused with a clear message.
- `verify --refill` against KiCad 10.0.8, with the buck project's own rules: 0.10.6 made one `copper_edge_clearance` DRC error. 0.10.7 makes none: it skips the step, because on that board no spot within 1 mm keeps the edge clearance on ground copper.
- Every command, on the new build:
  - `analyze --with all` on six real boards, compared finding by finding with 0.10.6.
  - `serve` and all 15 views in a headless browser, with no page errors from this release.
  - `tour`, `probe`, `report` and `parts`.
  - `thermal3d`, whose output is byte-identical to 0.10.6.
  - 0.10.6's fixes for issues 27, 28 and 29, re-run.

**Not checked:** the AM32 ESC board itself, whose page has the schematic but no board file; `silk`, which needs a kicad-cli SVG export not available here and is unchanged.