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John Lauer 0.10.2: PEEC decoupling-loop inductance in the pdn module (where the stackup allows) 6a8f94a

adom-fields 0.10.2

  • Decoupling loops solved from the copper (PEEC, in --with pdn).
    • What it solves: each capacitor's mounting inductance, as the loop from its pads through the board's copper and vias to the load pin and the load part's nearest ground pin.
    • The method: a partial-element equivalent circuit over every copper layer in a window around the loop, with three dielectric heights of margin and the cells coarsened to fit about 1,500 branches.
    • What it replaces: a distance estimate. mountModel says which was used and why, and mountNhEstimate keeps the estimate beside it.
    • Validation: a strip over a plane matches the 2-D field solve within 3 %. On the TPS54202 buck the loops are within 5 % of a large-window, fine-cell solve: the hot-loop capacitor C4 is about 2.0 nH where the estimate said 0.78 nH, and the input capacitors run 1.5 to 3 times the estimate. Four loops take about 7 s.
    • Where it does not solve yet: thin four-layer stackups (0.2 mm to the plane) need cells finer than this dense solver can afford, so their loops keep the estimate and say so.