Open bug report

Real vendor STEPs (ST/SamacSys VL53L5CX/L7CX/L8CX): Y-up pose rendered as-is, FoV-cone helper solids blow the bbox, VL53L8CX renders blank with ok:true

John Lauer · 1mo ago

Summary

adom-chip-thumbnailer once <MPN> (0.6.0) produces wrong chip icons and outlines for the three real ST/SamacSys STEPs it was handed (VL53L5CX, VL53L7CX, VL53L8CX, fetched from st.componentsearchengine.com), for three separate reasons that the tool could detect itself:

  1. The STEPs are Y-up (height along Y: bbox 6.40 x 1.50 x 3.03 mm). The "as-is (Z-up canonical)" pose renders the chip lying on its side, so the lasered name lands across the lens windows and the outline SVG is of the side face. The -yup.png orientation the tool already renders is the correct one (attached), but the outline SVGs and the -named icons are only produced for the as-is pose.
  2. Two near-zero-volume helper solids (the field-of-view cones ST ships, vol 0.03-0.05 mm3, 4.2-5.55 mm cubes) sit on top of the VL53L7CX and VL53L8CX bodies. They blow the bounding box to ~9.4 x 4.6 x 5.6 mm, the chip is framed tiny, and the red/blue cones dominate the icon (attached).
  3. VL53L8CX renders nothing at all (every -3d-iso*.png is 820 bytes: the bbox wireframe on the dark canvas, no body), and the named variant lasers the part number onto an empty cube. Exit 0, ok:true, no error in errors[].

VL53L5CX is also a surface model (0 solids, 38 open shells) rather than a solid; it still renders, so that one is only worth a note in the manifest.

Measured (CadQuery import of the same files)

VL53L5CX vendor  solids=0 shells=38 bbox x=6.40 y=1.50 z=3.03
VL53L7CX vendor  solids=4          bbox x=9.37 y=4.60 z=5.55
   solid1: 6.40 x 1.35 x 3.03  vol=24.83   <- body
   solid2: 5.55 x 3.00 x 5.55  vol=0.05    <- FoV cone (helper)
   solid3: 5.20 x 3.00 x 5.20  vol=0.04    <- FoV cone (helper)
VL53L8CX vendor  solids=4          bbox x=8.20 y=4.75 z=4.20
   solid1: 6.40 x 1.50 x 3.03  vol=26.88   <- body
   solid2/3: 4.20 x 3.00 x 4.20 vol=0.03   <- FoV cones

Proposals

  1. Auto-detect the up axis. For a package the thinnest bbox axis is the height; when it is Y (or X), rotate to Z-up before framing, lasering and outlining, and say so in _hints ("STEP was Y-up; rendered R_x(+pi/2)"). Also accept an explicit --up y|z and, when a .kicad_mod with a (model ... (rotate (xyz ...))) sits beside the STEP, honour that rotation.
  2. Ignore helper solids when framing. Drop solids whose volume is below ~1% of the largest solid (or below 0.5 mm3) from the bounding box and from the lasering/outline passes; render them faint or not at all. Report them in the manifest (helperSolids: [...]) so the caller knows.
  3. Never return ok:true for a blank render. If the rendered body covers < N pixels inside the bbox wireframe, fail with errorCode: empty_render and a hint (unit scale? shells only? tessellation failed?). The 820-byte PNG is a reliable tell.
  4. Put the vendor files in the response _hints when they are surface-only (0 solids) so the AI knows the outline is from open shells.

Repro

Attached: the three STEPs as fetched (renamed -cse-yup.step), plus VL53L5CX-3d-iso-named-debug.png (as-is, wrong), VL53L5CX-3d-iso-yup.png (correct pose), VL53L7CX-3d-iso-yup.png (cones), VL53L8CX-3d-iso-named-debug.png (blank). Run adom-chip-thumbnailer once VL53L8CX with the STEP copied to library/VL53L8CX/VL53L8CX.step.

Found while

Building the ToF 8x8 sensor library (adom-symbol chip thumbnails) on 2026-09-19; the datasheet-modelled Z-up STEPs render perfectly through the same pipeline, so the library shipped with those instead of the manufacturer files.

VL53L5CX-3d-iso-named-debug

VL53L5CX-3d-iso-yup

VL53L7CX-3d-iso-yup

VL53L8CX-3d-iso-named-debug

VL53L5CX-cse-yup.step

VL53L7CX-cse-yup.step

VL53L8CX-cse-yup.step

1 Reply

John Lauer · 1mo ago

Addendum from the same run (John's review of the shotlog, 2026-09-19): the -named / name-emboss variants laser the MPN across the TOP of these ToF modules, which covers the emitter/receiver windows and the gate grille, exactly the features the icon exists to show. For any package whose top carries optical windows, lenses, a grille, a marking pad or other identifying geometry, the only acceptable mark location is a clear SIDE WALL (the long wall facing the iso camera), sized to the wall height. Please:

  1. Detect a "busy top" (recess floors / windows / non-planar area above some fraction of the top face) and default the lasered name to the side wall, reporting markSurface: "side:-y" in the manifest and _hints.
  2. Accept an explicit --mark-surface top|side:-y|side:+y|side:-x|side:+x|none on once / rerender and on /name-emboss.
  3. When the top is busy and no side is chosen, do not emit the -named outline variant at all (an outline with text over the windows misleads every consumer), and say why in _hints.

Reference geometry: the VL53L5CX/L7CX/L8CX Z-up bodies are 6.4 x 3.0 x 1.5..1.75 mm; a 0.8 mm-high MPN fits the -y wall with margin. The derived side-etched STEPs used for the wiki pages (adom/vl53l5cx, vl53l7cx, vl53l8cx) show the placement.

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