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ADG3304SRUZ-EP-RL7

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Analog Devices Translators / Level Shifters, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADG3304SRUZ-EP-RL7

Analog Devices · Translators / Level Shifters · TSSOP-14

ADG3304SRUZ-EP-RL7 from Analog Devices, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCCA power_in Power supply voltage input for the A1 to A4 I/O pins, which must satisfy 1.15 V ≤ VCCA ≤ VCCY.
2 A1 bidirectional Input/output A1, referenced to VCCA.
3 A2 bidirectional Input/output A2, referenced to VCCA.
4 A3 bidirectional Input/output A3, referenced to VCCA.
5 A4 bidirectional Input/output A4, referenced to VCCA.
6 NC unconnected No connect.
7 GND power_in Ground reference, 0 V.
8 EN input Active high enable input referenced to VCCA; when pulled low, both the A and Y side terminals are placed in the high impedance state.
9 NC unconnected No connect.
10 Y4 bidirectional Input/output Y4, referenced to VCCY.
11 Y3 bidirectional Input/output Y3, referenced to VCCY.
12 Y2 bidirectional Input/output Y2, referenced to VCCY.
13 Y1 bidirectional Input/output Y1, referenced to VCCY.
14 VCCY power_in Power supply voltage input for the Y1 to Y4 I/O pins, 1.65 V ≤ VCC ≤ 5.5 V.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-14
Category Logic ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input High Voltage (A side), VCCA = 1.2 V + 0.1 V/−0.05 V VIHA 0.88 ×VCCA VCCA = 1.2 V + 0.1 V/−0.05 V 3
Input High Voltage (A side), VCCA = 1.8 V ± 0.15 V VIHA 0.72 ×VCCA VCCA = 1.8 V ± 0.15 V 3
Input High Voltage (A side), VCCA = 2.5 V ± 0.2 V VIHA 1.7 V VCCA = 2.5 V ± 0.2 V 3
Input High Voltage (A side), VCCA = 3.3 V ± 0.3 V VIHA 2.2 V VCCA = 3.3 V ± 0.3 V 3
Input High Voltage (A side), VCCA = 5 V ± 0.5 V VIHA 0.7 ×VCCA VCCA = 5 V ± 0.5 V 3
Input Low Voltage (A side), VCCA = 1.2 V + 0.1 V/−0.05 V VILA 0.35 ×VCCA VCCA = 1.2 V + 0.1 V/−0.05 V 3
Input Low Voltage (A side), VCCA = 1.8 V ± 0.15 V VILA 0.35 ×VCCA VCCA = 1.8 V ± 0.15 V 3
Input Low Voltage (A side), VCCA = 2.5 V ± 0.2 V VILA 0.7 V VCCA = 2.5 V ± 0.2 V 3
Input Low Voltage (A side), VCCA = 3.3 V ± 0.3 V VILA 0.8 V VCCA = 3.3 V ± 0.3 V 3
Input Low Voltage (A side), VCCA = 5 V ± 0.5 V VILA 0.3 ×VCCA VCCA = 5 V ± 0.5 V 3
Output Low Voltage (A side) VOLA 0.4 V VY = 0 V, IOL = 20 μA 3
Leakage Current (A side), Hi-Z ILA, Hi-Z -1 1 μA VA = 0 V/VCCA, EN = 0 3
Input High Voltage (Y side), VCCY = 1.8 V ± 0.15 V VIHY 0.67 ×VCCY VCCY = 1.8 V ± 0.15 V 3
Input High Voltage (Y side), VCCY = 2.5 V ± 0.2 V VIHY 1.7 V VCCY = 2.5 V ± 0.2 V 3
Input High Voltage (Y side), VCCY = 3.3 V ± 0.3 V VIHY 2 V VCCY = 3.3 V ± 0.3 V 3
Input High Voltage (Y side), VCCY = 5 V ± 0.5 V VIHY 0.7 ×VCCY VCCY = 5 V ± 0.5 V 3
Input Low Voltage (Y side), VCCY = 1.8 V ± 0.15 V VILY 0.35 ×VCCY VCCY = 1.8 V ± 0.15 V 3
Input Low Voltage (Y side), VCCY = 2.5 V ± 0.2 V VILY 0.7 V VCCY = 2.5 V ± 0.2 V 3
Input Low Voltage (Y side), VCCY = 3.3 V ± 0.3 V VILY 0.8 V VCCY = 3.3 V ± 0.3 V 3
Input Low Voltage (Y side), VCCY = 5 V ± 0.5 V VILY 0.25 ×VCCY VCCY = 5 V ± 0.5 V 3
Output Low Voltage (Y side) VOLY 0.4 V VA = 0 V, IOL = 20 μA 3
Leakage Current (Y side), Hi-Z ILY, Hi-Z -1 1 μA VY = 0 V/VCCY, EN = 0 3
Enable Input High Voltage, VCCA = 1.2 V + 0.1 V/−0.05 V VIHEN 0.88 ×VCCA VCCA = 1.2 V + 0.1 V/−0.05 V 3
Enable Input High Voltage, VCCA = 1.8 V ± 0.15 V VIHEN 0.72 ×VCCA VCCA = 1.8 V ± 0.15 V 3
Enable Input High Voltage, VCCA = 2.5 V ± 0.2 V VIHEN 1.7 V VCCA = 2.5 V ± 0.2 V 3
Enable Input High Voltage, VCCA = 3.3 V ± 0.3 V VIHEN 2.2 V VCCA = 3.3 V ± 0.3 V 3
Enable Input High Voltage, VCCA = 5 V ± 0.5 V VIHEN 0.7 ×VCCA VCCA = 5 V ± 0.5 V 3
Enable Input Low Voltage, VCCA = 1.2 V + 0.1 V/−0.05 V VILEN 0.35 ×VCCA VCCA = 1.2 V + 0.1 V/−0.05 V 3
Enable Input Low Voltage, VCCA = 1.8 V ± 0.15 V VILEN 0.35 ×VCCA VCCA = 1.8 V ± 0.15 V 3
Enable Input Low Voltage, VCCA = 2.5 V ± 0.2 V VILEN 0.7 V VCCA = 2.5 V ± 0.2 V 3
Enable Input Low Voltage, VCCA = 3.3 V ± 0.3 V VILEN 0.8 V VCCA = 3.3 V ± 0.3 V 3
Enable Input Low Voltage, VCCA = 5 V ± 0.5 V VILEN 0.3 ×VCCA VCCA = 5 V ± 0.5 V 3
Enable Leakage Current ILEN -1 1 μA VEN = 0 V/VCCA, VA = 0 V 3
Enable Time tEN 1 1.8 μs RS = RT = 50 Ω, VA = 0 V/VCCA (A→Y); VY = 0 V/VCCY (Y→A) 3
Power Supply Voltage VCCA VCCA 1.15 5.5 V VCCA ≤ VCCY 5
Power Supply Voltage VCCY VCCY 1.65 5.5 V 5
Quiescent Power Supply Current ICCA ICCA 0.17 5 μA VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 5
Quiescent Power Supply Current ICCY ICCY 0.27 5 μA VA = 0 V/VCCA, VY = 0 V/VCCY, VCCA = VCCY = 5.5 V, EN = 1 5
Three-State Mode Power Supply Current IHi-Z, A IHi-Z, A 0.1 5 μA VCCA = VCCY = 5.5 V, EN = 0 5
Three-State Mode Power Supply Current IHi-Z, Y IHi-Z, Y 0.1 5 μA VCCA = VCCY = 5.5 V, EN = 0 5
Operating Temperature Range TA -55 125 °C 6
Storage Temperature Range TSTG -65 150 °C 6
Junction Temperature TJ 150 °C 6
VCCA to GND VCCA -0.3 7 V 6
EN to GND EN -0.3 7 V 6
Thermal Impedance θJA, 14-Lead TSSOP θJA 112.6 °C/W 4-layer board 6
Propagation Delay tP, A→Y (3.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V) tP, A→Y 6 15 ns 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, RS = RT = 50 Ω, CL = 50 pF 4
Rise Time tR, A→Y (3.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V) tR, A→Y 2 5 ns 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, RS = RT = 50 Ω, CL = 50 pF 4
Fall Time tF, A→Y (3.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V) tF, A→Y 2 5 ns 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, RS = RT = 50 Ω, CL = 50 pF 4
Propagation Delay tP, Y→A (3.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V) tP, Y→A 4 10 ns 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, RS = RT = 50 Ω, CL = 15 pF 4
Rise Time tR, Y→A (3.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V) tR, Y→A 1 5 ns 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, RS = RT = 50 Ω, CL = 15 pF 4
Fall Time tF, Y→A (3.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V) tF, Y→A 3 10 ns 3.3 V ± 0.3 V ≤ VCCA ≤ VCCY, VCCY = 5 V ± 0.5 V, RS = RT = 50 Ω, CL = 15 pF 4
Propagation Delay tP, A→Y (1.8 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V) tP, A→Y 8 15 ns 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, RS = RT = 50 Ω, CL = 50 pF 4
Propagation Delay tP, Y→A (1.8 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V) tP, Y→A 5 12 ns 1.8 V ± 0.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, RS = RT = 50 Ω, CL = 15 pF 4
Propagation Delay tP, A→Y (1.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V) tP, A→Y 9 27 ns 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, RS = RT = 50 Ω, CL = 50 pF 4
Propagation Delay tP, Y→A (1.15 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V) tP, Y→A 5 13 ns 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, RS = RT = 50 Ω, CL = 15 pF 4
Propagation Delay tP, A→Y (1.15 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V) tP, A→Y 12 35 ns 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V, RS = RT = 50 Ω, CL = 50 pF 5
Propagation Delay tP, Y→A (1.15 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V) tP, Y→A 14 40 ns 1.15 V to 1.3 V ≤ VCCA ≤ VCCY, VCCY = 1.8 V ± 0.3 V, RS = RT = 50 Ω, CL = 15 pF 5
Propagation Delay tP, A→Y (2.5 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V) tP, A→Y 7 15 ns 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, RS = RT = 50 Ω, CL = 50 pF 5
Propagation Delay tP, Y→A (2.5 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V) tP, Y→A 5 12 ns 2.5 V ± 0.2 V ≤ VCCA ≤ VCCY, VCCY = 3.3 V ± 0.3 V, RS = RT = 50 Ω, CL = 15 pF 5

CAD (KiCad official)

  • Symbol: ADG3304SRUZ-EP-RL7
  • Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
  • 3D model: TSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: adg3304sruz-ep-rl7-etched.step / adg3304sruz-ep-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adg3304sruz-ep-rl7.step / adg3304sruz-ep-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (8 pp, sha256 4841f1e0ba6a4294, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF