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ADG1636BRUZ

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Analog Devices Pre-ordered Chips, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADG1636BRUZ

Analog Devices · Pre-ordered Chips · TSSOP-16

ADG1636BRUZ from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN1 input Logic control input for switch 1; the datasheet gives 3 V logic compatibility with VINH min 2.0 V and VINL max 0.8 V.
2 S1A bidirectional Source terminal of switch 1A, which can be an input or output and is connected to D1 when IN1 is logic 1.
3 D1 bidirectional Drain terminal of switch 1, which can be an input or output.
4 S1B bidirectional Source terminal of switch 1B, which can be an input or output and is connected to D1 when IN1 is logic 0.
5 VSS power_in Most negative power supply potential; the datasheet limits VDD to VSS to 18 V maximum.
6 GND power_in Ground (0 V) reference for the device.
7 NIC unconnected No internal connection; the pin is not connected inside the device.
8 NIC unconnected No internal connection; the pin is not connected inside the device.
9 IN2 input Logic control input for switch 2; the datasheet gives 3 V logic compatibility with VINH min 2.0 V and VINL max 0.8 V.
10 S2A bidirectional Source terminal of switch 2A, which can be an input or output and is connected to D2 when IN2 is logic 1.
11 D2 bidirectional Drain terminal of switch 2, which can be an input or output.
12 S2B bidirectional Source terminal of switch 2B, which can be an input or output and is connected to D2 when IN2 is logic 0.
13 VDD power_in Most positive power supply potential; the datasheet gives VDD to VSS absolute maximum of 18 V and VDD to GND of -0.3 V to +18 V.
14 EN input Active high digital enable input; when low, the device is disabled and all switches are off, and when high, the IN logic inputs determine the on switches.
15 NIC unconnected No internal connection; the pin is not connected inside the device.
16 NIC unconnected No internal connection; the pin is not connected inside the device.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Interface ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
On Resistance (RON) RON 1 1.6 Ω VS = ±4.5 V, IS = −10 mA; VDD = ±4.5 V, VSS = ±4.5 V 3
On Resistance Match Between Channels ∆RON 0.04 0.1 Ω VS = ±4.5 V, IS = −10 mA 3
On Resistance Flatness RFLAT(ON) 0.2 0.34 Ω VS = ±4.5 V, IS = −10 mA 3
Source Off Leakage IS (Off) -4 0.1 4 nA VS = ±4.5 V, VD = ∓4.5 V; see Figure 24 3
Drain Off Leakage ID (Off) -10 0.1 10 nA VS = ±4.5V, VD = ∓4.5 V; see Figure 24 3
Channel On Leakage ID, IS (On) -12 0.3 12 nA VS = VD = ±4.5 V; see Figure 25 3
Input High Voltage VINH 2 V 3
Input Low Voltage VINL 0.8 V 3
Input Current IINL or IINH -0.1 0.005 0.1 µA VIN = VGND or VDD 3
Transition Time tTRANSITION 130 273 ns RL = 300 Ω, CL = 35 pF; VS = 2.5 V; see Figure 30 3
Enable Turn-On Time tON (EN) 119 176 ns RL = 300 Ω, CL = 35 pF; VS = 2.5 V; see Figure 30 3
Enable Turn-Off Time tOFF (EN) 182 281 ns RL = 300 Ω, CL = 35 pF; VS = 2.5 V; see Figure 30 3
Break-Before-Make Time Delay tD 17 30 ns RL = 300 Ω, CL = 35 pF; VS1 = VS2 = 2.5 V; see Figure 31 3
Positive Supply Current IDD 0.001 1 µA Digital inputs = 0 V or VDD; VDD = +5.5 V, VSS = −5.5 V 3
Supply Range (dual supply) VDD/VSS 3.3 8 V Printed as ±3.3/±8 V min/max (dual supply) 3
On Resistance (RON) RON 0.95 1.45 Ω VS = 0 V to 10 V, IS = −10 mA; VDD = 10.8 V, VSS = 0 V 4
On Resistance Match Between Channels ∆RON 0.03 0.08 Ω VS = 10 V, IS = −10 mA 4
On Resistance Flatness RFLAT(ON) 0.2 0.32 Ω VS = 0 V to 10 V, IS = −10 mA 4
Source Off Leakage IS (Off) -4 0.1 4 nA VS = 1 V/10 V, VS = 10 V/1 V; see Figure 24 4
Drain Off Leakage ID (Off) -10 0.1 10 nA VS = 1 V/10 V, VS = 10 V/1 V; see Figure 24 4
Channel On Leakage ID, IS (On) -12 0.3 12 nA VS = VD = 1 V or 10 V; see Figure 25 4
Transition Time tTRANSITION 100 206 ns RL = 300 Ω, CL = 35 pF; VS = 8 V; see Figure 30 4
Enable Turn-On Time tON (EN) 80 110 ns RL = 300 Ω, CL = 35 pF; VS = 8 V; see Figure 30 4
Enable Turn-Off Time tOFF (EN) 133 210 ns RL = 300 Ω, CL = 35 pF; VS = 8 V; see Figure 30 4
Break-Before-Make Time Delay tD 17 25 ns RL = 300 Ω, CL = 35 pF; VS1 = VS2 = 8 V; see Figure 31 4
Positive Supply Current IDD 0.001 1 µA Digital inputs = 0 V or VDD; VDD = 12 V 4
Positive Supply Current (digital inputs high) IDD 230 360 µA Digital inputs = 5 V; VDD = 12 V 4
On Resistance (RON) RON 1.7 2.7 Ω VS = 0 V to 4.5V, IS = −10 mA; VDD = 4.5 V, VSS = 0 V 5
On Resistance Match Between Channels ∆RON 0.05 0.15 Ω VS = 0 V to 4.5 V, IS = −10 mA 5
On Resistance Flatness RFLAT(ON) 0.4 0.6 Ω VS = 0 V to 4.5 V, IS = −10 mA 5
Source Off Leakage IS (Off) -4 0.05 4 nA VS = 1V/4.5 V, VD = 4.5 V/1V; see Figure 24 5
Drain Off Leakage ID (Off) -10 0.05 10 nA VS = 1V/4.5 V, VD = 4.5 V/1V; see Figure 24 5
Channel On Leakage ID, IS (On) -12 0.1 12 nA VS = VD = 1 V or 4.5 V; see Figure 25 5
Transition Time tTRANSITION 160 355 ns RL = 300 Ω, CL = 35 pF; VS = 2.5 V; see Figure 30 5
Enable Turn-On Time tON (EN) 132 201 ns RL = 300 Ω, CL = 35 pF; VS = 2.5 V; see Figure 30 5
Enable Turn-Off Time tOFF (EN) 210 345 ns RL = 300 Ω, CL = 35 pF; VS = 2.5 V; see Figure 30 5
Break-Before-Make Time Delay tD 17 30 ns RL = 300 Ω, CL = 35 pF; VS1 = VS2 = 2.5 V; see Figure 31 5
Positive Supply Current IDD 0.001 1 µA Digital inputs = 0 V or VDD; VDD = 5.5 V 5
Supply Range VDD 3.3 16 V Printed as 3.3/16 V min/max; VDD = 5.5 V 5
Source Off Leakage IS (Off) -4 0.02 4 nA VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 24 6
Drain Off Leakage ID (Off) -10 0.02 10 nA VS = 0.6 V/3 V, VD = 3 V/0.6 V; see Figure 24 6
Channel On Leakage ID, IS (On) -12 0.05 12 nA VS = VD = 0.6 V or 3 V; see Figure 25 6
Transition Time tTRANSITION 275 550 ns RL = 300 Ω, CL = 35 pF; VS = 1.5 V; see Figure 30 6
Enable Turn-On Time tON (EN) 225 338 ns RL = 300 Ω, CL = 35 pF; VS = 1.5 V; see Figure 30 6
Enable Turn-Off Time tOFF (EN) 340 553 ns RL = 300 Ω, CL = 35 pF; VS = 1.5 V; see Figure 30 6
Break-Before-Make Time Delay tD 28 50 ns RL = 300 Ω, CL = 35 pF; VS1 = VS2 = 1.5 V; see Figure 31 6
Positive Supply Current IDD 0.001 1 µA Digital inputs = 0 V or VDD; VDD = 3.6 V 6
Continuous Current per Channel, S or D (TSSOP, 125°C) 88 mA VDD = +5 V, VSS = −5 V; TSSOP (θJA = 150.4°C/W); 125°C column 7
Continuous Current per Channel, S or D (TSSOP, 125°C) 98 mA VDD = 12 V, VSS = 0 V; TSSOP (θJA = 150.4°C/W); 125°C column 7
Continuous Current per Channel, S or D (TSSOP, 125°C) 77 mA VDD = 5 V, VSS = 0 V; TSSOP (θJA = 150.4°C/W); 125°C column 7
Continuous Current per Channel, S or D (TSSOP, 125°C) 84 mA VDD = 3.3 V, VSS = 0 V; TSSOP (θJA = 150.4°C/W); 125°C column 7
VDD to VSS VDD − VSS 18 V TA = 25°C, unless otherwise noted 8
VDD to GND VDD − GND -0.3 18 V TA = 25°C, unless otherwise noted 8
VSS to GND VSS − GND -18 0.3 V TA = 25°C, unless otherwise noted 8
Peak Current, S or D 850 mA Pulsed at 1 ms, 10% duty cycle maximum 8
Operating Temperature Range (Industrial, Y Version) -40 125 °C 8
Storage Temperature Range -65 150 °C 8
Junction Temperature 150 °C 8
Reflow Soldering Peak Temperature, Pb free 260 °C 8
Thermal Impedance, 16-Lead TSSOP (2-Layer Board) θJA 150.4 °C/W 16-Lead TSSOP (2-Layer Board) 8

CAD (KiCad official)

  • Symbol: ADG1636BRUZ
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: adg1636bruz-etched.step / adg1636bruz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adg1636bruz.step / adg1636bruz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (16 pp, sha256 78e3e239c1242588, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF