Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	7d ago
viewers	adf4158ccpz-rl7: viewers · Ray	7d ago
adf4158ccpz-rl7-etched.glb	Publish 0.1.0 · Ray	7d ago
adf4158ccpz-rl7-etched.step	adf4158ccpz-rl7: factory component page (tier=lcsc) · Ray	7d ago
adf4158ccpz-rl7-hero.glb	adf4158ccpz-rl7: hero GLB from the etched model (keeps the MPN mark) · Ray	7d ago
adf4158ccpz-rl7-hero.overlay.json	Publish 0.1.0 · Ray	7d ago
adf4158ccpz-rl7.glb	Publish 0.1.0 · Ray	7d ago
adf4158ccpz-rl7.kicad_mod	Publish 0.1.0 · Ray	7d ago
adf4158ccpz-rl7.kicad_sym	Publish 0.1.0 · Ray	7d ago
adf4158ccpz-rl7.lbr	Publish 0.1.0 · Ray	7d ago
adf4158ccpz-rl7.step	Publish 0.1.0 · Ray	7d ago
package.json	Publish 0.1.0 · Ray	7d ago
page.json	Set visibility: public · Ray	7d ago
README.md	Publish 0.1.0 · Ray	7d ago

ADF4158CCPZ-RL7

Analog Devices · Clock Generators, PLLs, Frequency Synthesizers · LFCSP-24(4x4)

ADF4158CCPZ-RL7 from Analog Devices, in a LFCSP-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CPGND	power_in	Charge pump ground; this is the ground return for the charge pump.
2	AGND	power_in	Analog ground; this is the ground return for the prescaler.
3	AGND	power_in	Analog ground; this is the ground return for the prescaler.
4	RFINB	input	Complementary RF prescaler input, decoupled to the ground plane through a small bypass capacitor (typically 100 pF).
5	RFINA	input	RF prescaler input; this small-signal input is normally AC-coupled from the VCO.
6	AVDD	power_in	Positive supply for the RF section; decouple to the digital ground plane close to the pin, and AVDD must be the same voltage as DVDD.
7	AVDD	power_in	Positive supply for the RF section; decouple to the digital ground plane close to the pin, and AVDD must be the same voltage as DVDD.
8	AVDD	power_in	Positive supply for the RF section; decouple to the digital ground plane close to the pin, and AVDD must be the same voltage as DVDD.
9	REFIN	input	Reference input; a CMOS input with a nominal threshold of VDD/2 and a 100 kΩ equivalent input resistance that can be driven by a TTL or CMOS crystal oscillator or AC-coupled.
10	DGND	power_in	Digital ground.
11	SDGND	power_in	Ground return for the digital sigma-delta modulator.
12	TXDATA	input	Tx data pin; supplies the data sent in FSK or PSK modulation mode.
13	CE	input	Chip enable; a logic low on this pin powers the device down and puts the charge pump output into three-state mode.
14	CLK	input	Serial clock input used to shift serial data into the register; data is latched into the shift register on the CLK rising edge, and this is a high-impedance CMOS input.
15	DATA	input	Serial data input, loaded MSB first with the three LSBs used as control bits; this is a high-impedance CMOS input.
16	LE	input	Load enable, CMOS input; when LE goes high, the data stored in the shift register is loaded into one of eight latches selected by the control bits.
17	MUXOUT	output	Multiplexer output allowing external access to RF lock detect, scaled RF, or reference frequency.
18	SDVDD	power_in	Power supply pin for the digital sigma-delta modulator; its voltage must equal AVDD, and a decoupling capacitor should be placed close to the pin.
19	DVDD	power_in	Positive supply for the digital section; decouple close to the pin, and DVDD must be the same voltage as AVDD.
20	SW1	passive	Switch used for fast lock.
21	SW2	passive	Switch used for fast lock.
22	VP	power_in	Charge pump supply; this pin must be greater than or equal to VDD, and in a 3 V system it can be set to 5.5 V to drive a VCO with a tuning range up to 5.5 V.
23	RSET	passive	A resistor connected between this pin and ground sets the maximum charge pump output current; the datasheet example gives ICPmax = 5 mA for RSET = 5.1 kΩ.
24	CP	output	Charge pump output; when enabled it supplies ±ICP to the external loop filter, which drives the external VCO.
25	EPAD	power_in	Exposed paddle on the LFCSP that must be connected to GND.

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-24(4x4)
Category	Clock/Timing
Pins	25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
RF input frequency (RFIN)	RFIN	0.5		6.1	GHz	−10 dBm (min) to 0 dBm (max)	4
REFIN input frequency	REFIN	10		260	MHz	If f < 10 MHz, use DC-coupled CMOS square wave, slew rate > 25 V/μs	4
REFIN input frequency (internal reference doubler enabled)	REFIN			16	MHz	If internal reference doubler enabled	4
REFIN input sensitivity		0.4			V p-p	Biased at AVDD/2	4
Phase frequency detector frequency				32	MHz		4
RSET range	RSET	2.7		10	kΩ		4
Charge pump three-state leakage current	ICP			1	nA	Sink and source current	4
Charge pump current matching	ICP			2	%	0.5 V < VCP < VP − 0.5 V	4
Charge pump current vs VCP	ICP			2	%	0.5 V < VCP < VP − 0.5 V	4
Charge pump current vs temperature	ICP			2	%	VCP = VP/2	4
Charge pump absolute accuracy	ICP			2.5	%	RSET = 5.1 kΩ	4
High input voltage	VINH	1.4			V		4
Low input voltage	VINL			0.6	V		4
Input current	IINH/IINL	-1		1	µA		4
High output voltage (open-drain output)	VOH	1.4			V	Open-drain output selected; 1 kΩ pull-up to 1.8 V	4
Output low voltage	VOL			0.4	V	IOL = 500 µA	4
High output current	IOH			100	µA		4
Supply voltage AVDD	AVDD	2.7		3.3	V		4
Charge pump supply voltage VP	VP			5.5	V		4
Supply current IDD	IDD		23	32	mA		4
Write timing LE setup time	t1	20			ns	TMIN to TMAX (grade C)	5
Write timing DATA to CLK setup time	t2	10			ns	TMIN to TMAX (grade C)	5
Write timing DATA to CLK hold time	t3	10			ns	TMIN to TMAX (grade C)	5
Write timing CLK high duration	t4	25			ns	TMIN to TMAX (grade C)	5
Write timing CLK low duration	t5	25			ns	TMIN to TMAX (grade C)	5
Write timing CLK to LE setup time	t6	10			ns	TMIN to TMAX (grade C)	5
Write timing LE pulse width	t7	20			ns	TMIN to TMAX (grade C)	5
Readback timing TXDATA setup time	t1	20			ns		6
Readback timing CLK to DATA (on MUXOUT) setup time	t2	20			ns		6
Readback timing CLK high duration	t3	25			ns		6
Readback timing CLK low duration	t4	25			ns		6
Readback timing CLK to LE setup time	t5	10			ns		6
VDD to GND	VDD	-0.3		4	V		7
VDD to VDD		-0.3		0.3	V		7
VP to GND	VP	-0.3		5.8	V		7
VP to VDD	VP	-0.3		5.8	V		7
Digital I/O voltage to GND		-0.3			V	Upper limit printed as VDD + 0.3 V	7
Analog I/O voltage to GND		-0.3			V	Upper limit printed as VDD + 0.3 V	7
REFIN, RFIN to GND		-0.3			V	Upper limit printed as VDD + 0.3 V	7
Operating temperature range (industrial, grade C)	TA	-40		125	°C		7
Storage temperature range	TSTG	-65		125	°C		7
Maximum junction temperature	TJ			150	°C		7
LFCSP thermal resistance junction-to-ambient	θJA		30.4		°C/W	Exposed pad soldered	7
Reflow peak temperature				260	°C		7
Peak temperature time (reflow)				40	sec		7

CAD (KiCad official)

Symbol: ADF4158CCPZ-RL7
Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
3D model: LFCSP-24(4x4) (KiCad packages3D, STEP)
3D model files: adf4158ccpz-rl7-etched.step / adf4158ccpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adf4158ccpz-rl7.step / adf4158ccpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (36 pp, sha256 7b6bbb25f289e954, retrieved 2026-10-20, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF