ADC141S626CIMM

Texas Instruments · Analog To Digital Converters (ADC) · VSSOP-10-0.5mm

ADC141S626CIMM from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VREF	power_in	Voltage reference input that must be driven with a reference between 1 V and VA and decoupled to GND with at least 0.1 µF ceramic, with 1.0 µF to 10 µF bulk capacitance recommended in parallel.
2	+IN	input	Non-inverting positive analog input of the differential signal, with analog input voltage range 0 to VA.
3	-IN	input	Inverting negative analog input of the differential signal, with analog input voltage range 0 to VA.
4	GND	power_in	Ground reference point for all signals applied to the ADC141S626.
5	GND	power_in	Ground reference point for all signals applied to the ADC141S626.
6	CS	input	Active-LOW chip select: CS must be LOW during an SPI conversion, which starts on the CS falling edge, and the device is in acquisition mode while CS is HIGH.
7	DOUT	output	Serial data output carrying 2 null bits followed by 14 data bits MSB first, updated on SCLK falling edges and valid on the following rising edges.
8	SCLK	input	Serial clock that controls data transfer and serves as the conversion clock, operating over 0.9 MHz to 4.5 MHz.
9	VIO	power_in	Digital I/O supply input that must be applied between 2.7 V and 5.5 V and decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk capacitance.
10	VA	power_in	Analog supply input that must be applied between 2.7 V and 5.5 V and decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk capacitance.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	VSSOP-10-0.5mm
Category	Data Acquisition
Pins	10

CAD (KiCad official)

Symbol: ADC141S626CIMM
Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
3D model files: adc141s626cimm-etched.step / adc141s626cimm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc141s626cimm.step / adc141s626cimm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (30 pp, sha256 b3be444a781e8118, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# ADC141S626CIMM

**Texas Instruments** · Analog To Digital Converters (ADC) · VSSOP-10-0.5mm

ADC141S626CIMM from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Voltage reference input that must be driven with a reference between 1 V and VA and decoupled to GND with at least 0.1 µF ceramic, with 1.0 µF to 10 µF bulk capacitance recommended in parallel. |
| 2 | +IN | input | Non-inverting positive analog input of the differential signal, with analog input voltage range 0 to VA. |
| 3 | -IN | input | Inverting negative analog input of the differential signal, with analog input voltage range 0 to VA. |
| 4 | GND | power_in | Ground reference point for all signals applied to the ADC141S626. |
| 5 | GND | power_in | Ground reference point for all signals applied to the ADC141S626. |
| 6 | CS | input | Active-LOW chip select: CS must be LOW during an SPI conversion, which starts on the CS falling edge, and the device is in acquisition mode while CS is HIGH. |
| 7 | DOUT | output | Serial data output carrying 2 null bits followed by 14 data bits MSB first, updated on SCLK falling edges and valid on the following rising edges. |
| 8 | SCLK | input | Serial clock that controls data transfer and serves as the conversion clock, operating over 0.9 MHz to 4.5 MHz. |
| 9 | VIO | power_in | Digital I/O supply input that must be applied between 2.7 V and 5.5 V and decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk capacitance. |
| 10 | VA | power_in | Analog supply input that must be applied between 2.7 V and 5.5 V and decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk capacitance. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Data Acquisition |
| Pins | 10 |

## CAD (KiCad official)

- Symbol: `ADC141S626CIMM`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files: `adc141s626cimm-etched.step` / `adc141s626cimm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc141s626cimm.step` / `adc141s626cimm.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc141s626) (30 pp, sha256 `b3be444a781e8118`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/adc141s626cimm-datasheet.pdf)