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Initial commit: component/adc141s626cimm

Ray ·adc34b67cb ·1d ago
2 files changed +255
README.mdadded+46
@@ -0,0 +1,46 @@+# ADC141S626CIMM++**Texas Instruments** · Analog To Digital Converters (ADC) · VSSOP-10-0.5mm++ADC141S626CIMM from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VREF | power_in | Voltage reference input that must be driven with a reference between 1 V and VA and decoupled to GND with at least 0.1 µF ceramic, with 1.0 µF to 10 µF bulk capacitance recommended in parallel. |+| 2 | +IN | input | Non-inverting positive analog input of the differential signal, with analog input voltage range 0 to VA. |+| 3 | -IN | input | Inverting negative analog input of the differential signal, with analog input voltage range 0 to VA. |+| 4 | GND | power_in | Ground reference point for all signals applied to the ADC141S626. |+| 5 | GND | power_in | Ground reference point for all signals applied to the ADC141S626. |+| 6 | CS | input | Active-LOW chip select: CS must be LOW during an SPI conversion, which starts on the CS falling edge, and the device is in acquisition mode while CS is HIGH. |+| 7 | DOUT | output | Serial data output carrying 2 null bits followed by 14 data bits MSB first, updated on SCLK falling edges and valid on the following rising edges. |+| 8 | SCLK | input | Serial clock that controls data transfer and serves as the conversion clock, operating over 0.9 MHz to 4.5 MHz. |+| 9 | VIO | power_in | Digital I/O supply input that must be applied between 2.7 V and 5.5 V and decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk capacitance. |+| 10 | VA | power_in | Analog supply input that must be applied between 2.7 V and 5.5 V and decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk capacitance. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | VSSOP-10-0.5mm |+| Category | Data Acquisition |+| Pins | 10 |++## CAD (KiCad official)++- Symbol: `ADC141S626CIMM`+- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`+- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)+- 3D model files: `adc141s626cimm-etched.step` / `adc141s626cimm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc141s626cimm.step` / `adc141s626cimm.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc141s626) (30 pp, sha256 `b3be444a781e8118`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/adc141s626cimm-datasheet.pdf)
page.jsonadded+209
@@ -0,0 +1,209 @@+{+  "slug": "adc141s626cimm",+  "version": "0.1.0",+  "type": "component",+  "description": "Texas Instruments Analog To Digital Converters (ADC), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+  "tags": [+    "component",+    "data acquisition",+    "adc141s626cimm",+    "factory-2.0.0",+    "extractor-text"+  ],+  "dependencies": {},+  "hero": {+    "type": "image",+    "path": "docs/hero.png"+  },+  "files": [+    "page.json",+    "README.md",+    "adc141s626cimm.kicad_sym",+    "adc141s626cimm.kicad_mod",+    "adc141s626cimm.glb",+    "adc141s626cimm.step",+    "adc141s626cimm.lbr",+    "docs/hero.png",+    "docs/adc141s626cimm-datasheet.pdf",+    "viewers/symbol.html",+    "viewers/footprint.html",+    "adc141s626cimm-hero.glb",+    "adc141s626cimm-hero.overlay.json"+  ],+  "component": {+    "mpn": "ADC141S626CIMM",+    "manufacturer": "Texas Instruments",+    "package": "VSSOP-10-0.5mm",+    "pin_count": 10,+    "category": "Data Acquisition",+    "subcategory": "Analog To Digital Converters (ADC)",+    "datasheet": "https://www.ti.com/cn/lit/gpn/adc141s626",+    "parts": {+      "symbol": "adc141s626cimm.kicad_sym",+      "footprint": "adc141s626cimm.kicad_mod",+      "model_3d": "adc141s626cimm-hero.glb",+      "model_3d_plain": "adc141s626cimm.glb",+      "model_3d_step": "adc141s626cimm-etched.step",+      "model_3d_step_plain": "adc141s626cimm.step",+      "lbr": "adc141s626cimm.lbr"+    },+    "distributor_links": {+      "lcsc": "C206494"+    },+    "distributor_check": {+      "checked_at": "2026-10-08T03:20:18Z",+      "source": "Component Ocean /api/assign-pns",+      "digikey": {+        "pn": null,+        "status": "no match"+      },+      "mouser": {+        "pn": null,+        "status": "no match"+      }+    },+    "pins": [+      {+        "number": "1",+        "name": "VREF",+        "type": "power_in",+        "description": "Voltage reference input that must be driven with a reference between 1 V and VA and decoupled to GND with at least 0.1 µF ceramic, with 1.0 µF to 10 µF bulk capacitance recommended in parallel."+      },+      {+        "number": "2",+        "name": "+IN",+        "type": "input",+        "description": "Non-inverting positive analog input of the differential signal, with analog input voltage range 0 to VA."+      },+      {+        "number": "3",+        "name": "-IN",+        "type": "input",+        "description": "Inverting negative analog input of the differential signal, with analog input voltage range 0 to VA."+      },+      {+        "number": "4",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference point for all signals applied to the ADC141S626."+      },+      {+        "number": "5",+        "name": "GND",+        "type": "power_in",+        "description": "Ground reference point for all signals applied to the ADC141S626."+      },+      {+        "number": "6",+        "name": "CS",+        "type": "input",+        "description": "Active-LOW chip select: CS must be LOW during an SPI conversion, which starts on the CS falling edge, and the device is in acquisition mode while CS is HIGH."+      },+      {+        "number": "7",+        "name": "DOUT",+        "type": "output",+        "description": "Serial data output carrying 2 null bits followed by 14 data bits MSB first, updated on SCLK falling edges and valid on the following rising edges."+      },+      {+        "number": "8",+        "name": "SCLK",+        "type": "input",+        "description": "Serial clock that controls data transfer and serves as the conversion clock, operating over 0.9 MHz to 4.5 MHz."+      },+      {+        "number": "9",+        "name": "VIO",+        "type": "power_in",+        "description": "Digital I/O supply input that must be applied between 2.7 V and 5.5 V and decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk capacitance."+      },+      {+        "number": "10",+        "name": "VA",+        "type": "power_in",+        "description": "Analog supply input that must be applied between 2.7 V and 5.5 V and decoupled to GND with 0.1 µF ceramic in parallel with 1.0 µF to 10 µF bulk capacitance."+      }+    ],+    "provenance": {+      "extractor": "extract_pins 0.3",+      "factory_chain": {+        "factory": "2.0.0",+        "extractor": "extract_pins 0.3",+        "primary_model": "claude-haiku-5-5",+        "primary_mode": "text",+        "consensus_model": "claude-sonnet-5-5",+        "consensus": "agreed",+        "guards": "pin_guards 0.1: passed",+        "guard_notes": [+          "extractor flagged: The Connection Diagram text in the extracted datasheet is scrambled, so pin numbers were taken from ; Package confirmed: the page 24 package addendum lists ADC141S626CIMM/NOPB and ADC141S626CIMM/NO.A as"+        ],+        "pages_sent": 6,+        "cost_usd": 0.0471,+        "at": "2026-10-08T03:20:02"+      },+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/adc141s626",+        "pages": 30,+        "sha256": "b3be444a781e8118",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 10,+        "described": 10,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    },+    "models_3d": [+      {+        "file": "adc141s626cimm.step",+        "role": "plain",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          4.9,+          3,+          1.1+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "b8f88eac3ce221c2ccb0b5048f9ad49c2ef4af148f8ae50c4e232e357683f547",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      },+      {+        "file": "adc141s626cimm-etched.step",+        "role": "eda",+        "up": "Z",+        "units": "mm",+        "origin": "footprint origin = pad-pattern centre",+        "seat": "z = 0",+        "extents_mm": [+          4.9,+          3,+          1.1+        ],+        "zmin_mm": 0,+        "centre_offset_mm": 0,+        "footprint_binding": "identity",+        "sha256": "f1258c4024cb54fcb7d823665e56163c53a37f31f858172e06226430e5425680",+        "checked": "2026-10-08",+        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+      }+    ]+  },+  "visibility": "public",+  "org": "adom",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  }+}\ No newline at end of file