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ADC12L066CIVY

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Texas Instruments Analog To Digital Converters (ADC), TQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADC12L066CIVY

Texas Instruments · Analog To Digital Converters (ADC) · TQFP-32(7x7)

ADC12L066CIVY from Texas Instruments, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VREF power_in Reference input bypassed to AGND with a 0.1 µF monolithic capacitor; VREF is 1.0 V nominal and should be between 0.8 V and 1.5 V.
2 VIN+ power_in Positive analog signal input; with VREF = 1.0 V the differential input is 2.0 VP-P, and the input peaks should never exceed VA − 0.8 V.
3 VIN- power_in Negative analog signal input that may be tied to VCM for single-ended operation, but a differential input signal is required for best performance.
4 AGND power_in Ground return for the analog supply.
5 VA power_in Positive analog supply, operated from +3.0 V to +3.6 V and bypassed to AGND with a 0.1 µF capacitor within 1 cm plus a 10 µF capacitor.
6 VA power_in Positive analog supply, operated from +3.0 V to +3.6 V and bypassed to AGND with a 0.1 µF capacitor within 1 cm plus a 10 µF capacitor.
7 AGND power_in Ground return for the analog supply.
8 PD input Power-down input; when high the converter is held in power-down mode (50 mW with a 66 MHz clock), and when low it is in active mode.
9 DGND power_in Ground return for the digital supply.
10 CLK input Clock input with a range of 1 MHz to 80 MHz (typical), specified performance at 66 MHz, sampled on the rising edge.
11 OE input Output enable; when low the TRI-STATE data outputs are enabled, and when high they are placed in a high impedance state.
12 DGND power_in Ground return for the digital supply.
13 VD power_in Positive digital supply, connected to the same quiet +3.3 V source as VA and bypassed to DGND with a 0.1 µF capacitor in parallel with a 10 µF capacitor within 1 cm of the pin.
14 D0 tri_state Digital output bit 0 (LSB) of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
15 D1 tri_state Digital output bit 1 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
16 D2 tri_state Digital output bit 2 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
17 D3 tri_state Digital output bit 3 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
18 D4 tri_state Digital output bit 4 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
19 D5 tri_state Digital output bit 5 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
20 DR GND power_in Ground return for the digital supply of the output drivers, to be connected to system digital ground and not in close proximity to the DGND or AGND pins.
21 VDR power_in Positive supply for the output drivers, from +1.8 V to VD, which must never exceed VD by more than 300 mV.
22 D6 tri_state Digital output bit 6 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
23 D7 tri_state Digital output bit 7 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
24 D8 tri_state Digital output bit 8 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
25 D9 tri_state Digital output bit 9 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
26 D10 tri_state Digital output bit 10 of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
27 D11 tri_state Digital output bit 11 (MSB) of the 12-bit offset binary conversion result, TTL/CMOS compatible and TRI-STATE controlled by OE.
28 AGND power_in Ground return for the analog supply.
29 VA power_in Positive analog supply, operated from +3.0 V to +3.6 V and bypassed to AGND with a 0.1 µF capacitor within 1 cm plus a 10 µF capacitor.
30 VRN passive High impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; nominal voltage VRM − VREF/2; do not load.
31 VRP passive High impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; nominal voltage VRM + VREF/2; do not load.
32 VRM passive High impedance reference bypass pin, bypassed to AGND with a 0.1 µF capacitor; nominal voltage VA/2; do not load.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TQFP-32(7x7)
Category Data Acquisition
Pins 32

CAD (KiCad official)

  • Symbol: ADC12L066CIVY
  • Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
  • 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: adc12l066civy-etched.step / adc12l066civy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adc12l066civy.step / adc12l066civy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (38 pp, sha256 6f1f3b8cb7bb0b75, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF