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ADC122S655CIMM
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Texas Instruments Global Sourcing Parts, VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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ADC122S655CIMM
Texas Instruments · Global Sourcing Parts · VSSOP-10-0.5mm
ADC122S655CIMM from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Voltage reference input that must be driven between 1V and VA, and decoupled to GND with a minimum 0.1 µF ceramic capacitor (1.0 µF to 10 µF bulk in parallel recommended). |
| 2 | CHA+ | input | Non-inverting analog input for Channel A, the positive side of the differential signal applied to Channel A. |
| 3 | CHA- | input | Inverting analog input for Channel A, the negative side of the differential signal applied to Channel A. |
| 4 | CHB- | input | Inverting analog input for Channel B, the negative side of the differential signal applied to Channel B. |
| 5 | CHB+ | input | Non-inverting analog input for Channel B, the positive side of the differential signal applied to Channel B. |
| 6 | GND | power_in | Ground reference point for all signals applied to the ADC122S655. |
| 7 | VA | power_in | Analog power supply input that must be held between 4.5V and 5.5V and decoupled to GND with a minimum 0.1 µF ceramic capacitor (1.0 µF to 10 µF bulk in parallel recommended). |
| 8 | DOUT | output | Serial data output for both channels, carrying 4 null bits, 12 bits of Channel A, 4 null bits and 12 bits of Channel B, updated on SCLK falling edges and valid on rising edges. |
| 9 | SCLK | input | Serial clock that controls data transfer and serves as the conversion clock, with a specified range of 6.4 MHz to 16 MHz. |
| 10 | CS | input | Active-low chip select: the device converts while CS is low, enters power-down while CS is high, and a conversion begins on the falling edge of CS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Global Sourcing Parts |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
ADC122S655CIMM - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files:
adc122s655cimm-etched.step/adc122s655cimm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adc122s655cimm.step/adc122s655cimm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (29 pp, sha256
fc23d6f6c33bbd16, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# ADC122S655CIMM
**Texas Instruments** · Global Sourcing Parts · VSSOP-10-0.5mm
ADC122S655CIMM from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Voltage reference input that must be driven between 1V and VA, and decoupled to GND with a minimum 0.1 µF ceramic capacitor (1.0 µF to 10 µF bulk in parallel recommended). |
| 2 | CHA+ | input | Non-inverting analog input for Channel A, the positive side of the differential signal applied to Channel A. |
| 3 | CHA- | input | Inverting analog input for Channel A, the negative side of the differential signal applied to Channel A. |
| 4 | CHB- | input | Inverting analog input for Channel B, the negative side of the differential signal applied to Channel B. |
| 5 | CHB+ | input | Non-inverting analog input for Channel B, the positive side of the differential signal applied to Channel B. |
| 6 | GND | power_in | Ground reference point for all signals applied to the ADC122S655. |
| 7 | VA | power_in | Analog power supply input that must be held between 4.5V and 5.5V and decoupled to GND with a minimum 0.1 µF ceramic capacitor (1.0 µF to 10 µF bulk in parallel recommended). |
| 8 | DOUT | output | Serial data output for both channels, carrying 4 null bits, 12 bits of Channel A, 4 null bits and 12 bits of Channel B, updated on SCLK falling edges and valid on rising edges. |
| 9 | SCLK | input | Serial clock that controls data transfer and serves as the conversion clock, with a specified range of 6.4 MHz to 16 MHz. |
| 10 | CS | input | Active-low chip select: the device converts while CS is low, enters power-down while CS is high, and a conversion begins on the falling edge of CS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Global Sourcing Parts |
| Pins | 10 |
## CAD (KiCad official)
- Symbol: `ADC122S655CIMM`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files: `adc122s655cimm-etched.step` / `adc122s655cimm-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `adc122s655cimm.step` / `adc122s655cimm.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/adc122s655) (29 pp, sha256 `fc23d6f6c33bbd16`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/adc122s655cimm-datasheet.pdf)