ADC108S022CIMT

{
  "slug": "adc108s022cimt",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "adc-dac-data conversion",
    "adc108s022cimt",
    "factory-2.0.0",
    "extractor-text"
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  "component": {
    "mpn": "ADC108S022CIMT",
    "manufacturer": "Texas Instruments",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Analog To Digital Converters (ADCs)",
    "datasheet": "https://www.ti.com/cn/lit/gpn/adc108s022",
    "parts": {
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      "model_3d_plain": "adc108s022cimt.glb",
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      "model_3d_step_plain": "adc108s022cimt.step",
      "lbr": "adc108s022cimt.lbr"
    },
    "distributor_links": {
      "lcsc": "C183101",
      "digikey": "ADC108S022CIMT-ND",
      "mouser": "926-ADC108S022CIMT"
    },
    "distributor_check": {
      "checked_at": "2026-10-10T16:03:09Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "ADC108S022CIMT-ND",
        "status": "found",
        "lifecycle": "Obsolete"
      },
      "mouser": {
        "pn": "926-ADC108S022CIMT",
        "status": "found",
        "lifecycle": "Obsolete"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "CS",
        "type": "input",
        "description": "Chip select: a conversion begins on the falling edge of CS and conversions continue as long as CS is held low."
      },
      {
        "number": "2",
        "name": "VA",
        "type": "power_in",
        "description": "Positive analog supply, also used as the reference voltage; connect to a quiet +2.7V to +5.25V source and bypass to GND with 1 µF and 0.1 µF ceramic capacitors within 1 cm of the pin."
      },
      {
        "number": "3",
        "name": "AGND",
        "type": "power_in",
        "description": "Ground return for the analog supply and signals."
      },
      {
        "number": "4",
        "name": "IN0",
        "type": "input",
        "description": "Analog input channel 0; signals can range from 0V to VREF."
      },
      {
        "number": "5",
        "name": "IN1",
        "type": "input",
        "description": "Analog input channel 1; signals can range from 0V to VREF."
      },
      {
        "number": "6",
        "name": "IN2",
        "type": "input",
        "description": "Analog input channel 2; signals can range from 0V to VREF."
      },
      {
        "number": "7",
        "name": "IN3",
        "type": "input",
        "description": "Analog input channel 3; signals can range from 0V to VREF."
      },
      {
        "number": "8",
        "name": "IN4",
        "type": "input",
        "description": "Analog input channel 4; signals can range from 0V to VREF."
      },
      {
        "number": "9",
        "name": "IN5",
        "type": "input",
        "description": "Analog input channel 5; signals can range from 0V to VREF."
      },
      {
        "number": "10",
        "name": "IN6",
        "type": "input",
        "description": "Analog input channel 6; signals can range from 0V to VREF."
      },
      {
        "number": "11",
        "name": "IN7",
        "type": "input",
        "description": "Analog input channel 7; signals can range from 0V to VREF."
      },
      {
        "number": "12",
        "name": "DGND",
        "type": "power_in",
        "description": "Ground return for the digital supply and signals."
      },
      {
        "number": "13",
        "name": "VD",
        "type": "power_in",
        "description": "Positive digital supply, to be connected to +2.7V up to VA and bypassed to GND with a 0.1 µF ceramic capacitor within 1 cm of the pin."
      },
      {
        "number": "14",
        "name": "DIN",
        "type": "input",
        "description": "Digital data input through which the Control Register is loaded on rising edges of SCLK."
      },
      {
        "number": "15",
        "name": "DOUT",
        "type": "output",
        "description": "Digital data output; output samples are clocked out on the falling edges of SCLK."
      },
      {
        "number": "16",
        "name": "SCLK",
        "type": "input",
        "description": "Digital clock input with an ensured performance range of 0.8 MHz to 3.2 MHz that directly controls the conversion and readout processes."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet pin table gives IN0 to IN7 as the range 'pins 4 - 11' rather than one number per chann; The datasheet does not state a separate pinout per orderable variant. The package addendum (page 20); The schema has no field for electrical specs, so the headline ratings (VA 2.7V to 5.25V, operating t"
        ],
        "pages_sent": 6,
        "cost_usd": 0.0382,
        "at": "2026-10-10T16:02:51"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/adc108s022",
        "pages": 28,
        "sha256": "342a6a6d1a21a391",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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}