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ADC108S022CIMT
Public Made by Adomby adom
Texas Instruments Analog To Digital Converters (ADCs), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownADC108S022CIMT
Texas Instruments · Analog To Digital Converters (ADCs) · TSSOP-16
ADC108S022CIMT from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS | input | Chip select: a conversion begins on the falling edge of CS and conversions continue as long as CS is held low. |
| 2 | VA | power_in | Positive analog supply, also used as the reference voltage; connect to a quiet +2.7V to +5.25V source and bypass to GND with 1 µF and 0.1 µF ceramic capacitors within 1 cm of the pin. |
| 3 | AGND | power_in | Ground return for the analog supply and signals. |
| 4 | IN0 | input | Analog input channel 0; signals can range from 0V to VREF. |
| 5 | IN1 | input | Analog input channel 1; signals can range from 0V to VREF. |
| 6 | IN2 | input | Analog input channel 2; signals can range from 0V to VREF. |
| 7 | IN3 | input | Analog input channel 3; signals can range from 0V to VREF. |
| 8 | IN4 | input | Analog input channel 4; signals can range from 0V to VREF. |
| 9 | IN5 | input | Analog input channel 5; signals can range from 0V to VREF. |
| 10 | IN6 | input | Analog input channel 6; signals can range from 0V to VREF. |
| 11 | IN7 | input | Analog input channel 7; signals can range from 0V to VREF. |
| 12 | DGND | power_in | Ground return for the digital supply and signals. |
| 13 | VD | power_in | Positive digital supply, to be connected to +2.7V up to VA and bypassed to GND with a 0.1 µF ceramic capacitor within 1 cm of the pin. |
| 14 | DIN | input | Digital data input through which the Control Register is loaded on rising edges of SCLK. |
| 15 | DOUT | output | Digital data output; output samples are clocked out on the falling edges of SCLK. |
| 16 | SCLK | input | Digital clock input with an ensured performance range of 0.8 MHz to 3.2 MHz that directly controls the conversion and readout processes. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | ADC/DAC/Data Conversion |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
ADC108S022CIMT - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
adc108s022cimt-etched.step/adc108s022cimt-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);adc108s022cimt.step/adc108s022cimt.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (28 pp, sha256
342a6a6d1a21a391, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).