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ADAU7118ACPZRL

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Analog Devices Analog To Digital Converters (ADC), LFCSP-16(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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ADAU7118ACPZRL

Analog Devices · Analog To Digital Converters (ADC) · LFCSP-16(3x3)

ADAU7118ACPZRL from Analog Devices, in a LFCSP-16(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PDM_CLK0 output PDM output clock 0, with output drive strength set by PDM_CLK0_DS (2.5 mA to 15 mA at 3.3 V).
2 PDM_DAT0 input PDM input data 0 from the digital microphone(s) on this channel pair.
3 PDM_DAT1 input PDM input data 1 from the digital microphone(s) on this channel pair.
4 PDM_CLK1 output PDM output clock 1, with output drive strength set by PDM_CLK1_DS (2.5 mA to 15 mA at 3.3 V).
5 PDM_DAT2 input PDM input data 2 from the digital microphone(s) on this channel pair.
6 PDM_DAT3 input PDM input data 3 from the digital microphone(s) on this channel pair.
7 SCL input I2C serial clock input; the pin is open-drain and requires pull-up resistors to IOVDD.
8 SDA bidirectional I2C serial data; the pin is open-drain and requires pull-up resistors to IOVDD.
9 FSYNC input I2S/TDM frame sync or left/right clock, used as the slave frame sync input.
10 BCLK input I2S/TDM bit clock input, which the device uses as a slave clock; BCLK removal automatically powers the device down.
11 SDATA output I2S/TDM serial data output, with output drive strength set by SDATA_DS (2.5 mA to 15 mA at 3.3 V).
12 ADDR/CONFIG input I2C address or standalone hardware configuration selection, set by tying the pin to IOVDD, GND, through a 47 kΩ resistor, or leaving it open.
13 EN input Chip enable; grounding this pin disables the device into low power mode, and applying IOVDD enables normal operation.
14 DVDD power_in Internal core digital power supply, 1.10 V to 1.98 V.
15 GND power_in Ground.
16 IOVDD power_in Digital input/output power supply, 1.70 V to 3.63 V.
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-16(3x3)
Category Data Acquisition
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital Voltage (DVDD Pin) supply 1.1 1.98 V Supply for digital circuitry 3
I/O Supply Voltage (IOVDD Pin) 1.7 3.63 V Supply for input/output circuitry, including pads and level shifters 4
Operating ambient temperature range TA -40 85 °C Commercial temperature range 1
Output Sampling Rate fS 4 48 192 kHz FSYNC pulse rate 4
Bit Clock Frequency fBCLK 0.256 12.288 24.576 MHz 4
PDM_CLKx Frequency fPDM_CLK 0.256 3.072 6.144 MHz 4
IOVDD operating current (Operation State) 2 mA IOVDD = 3.3 V, 48 kHz fS, TDM-8 format, all channels driven, default drive strength, 25 pF capacitance, only one PDM_CLKx pin used 4
DVDD operating current (Operation State) 1.4 mA Over all temperatures, full voltage range and silicon skews, 8 channels, 48 kHz fS 4
DVDD operating current (Operation State) 1.2 mA DVDD = 1.8 V, 8 channels, 48 kHz fS 4
Shutdown current 16 µA Power applied, frame and bit clocks applied, device placed into power-down state using procedure in Table 10 4
Shutdown current 3 µA Power applied, frame and bit clocks applied, device placed into power-down state using procedure in Table 9 4
Frequency Response -0.1 0.01 dB DC to 0.45 × output sampling rate (fS) 3
Gain 0 0 0 dB PDM to PCM 4
Group Delay 4.47 4.47 4.47 FSYNC cycles 0.02 fS input signal, 64× decimation 3
Group Delay 5.02 5.02 5.02 FSYNC cycles 0.02 fS input signal, 32× decimation 3
Group Delay 5.83 5.83 5.83 FSYNC cycles 0.02 fS input signal, 16× decimation 3
Start-Up Time 63 64 64 FSYNC cycles After power-up reset and initialization code runs 4
Interchannel Phase 0 0 0 Degrees 4
High-Pass Filter −3 dB Point 0.23328 0.9312 242.4 Hz fS = 48 kHz, cutoff frequency set using the HPF_FC bits in the HPF_CONTROL register, typical value is default setting 4
FSYNC frequency fFSYNC 192 kHz 5
BCLK frequency fBCLK 24.576 MHz Sample rate ranging from 4 kHz to 192 kHz 5
BCLK period tBCLK 40.7 ns 5
BCLK low pulse width tBIL 18 ns Slave mode, BCLK frequency = 24.576 MHz, BCLK period = 40.6 ns 5
BCLK high pulse width tBIH 18 ns Slave mode, BCLK frequency = 24.576 MHz, BCLK period = 40.6 ns 5
FSYNC setup to BCLK input rising edge tLIS 10 ns Slave mode, FSYNC frequency = 192 kHz 5
FSYNC hold from BCLK input rising edge tLIH 10 ns Slave mode, FSYNC frequency = 192 kHz 5
SDATA delay from BCLK output falling edge tSOD 20.63 ns 25 pF load over entire range of IOVDD, all temperatures and skews, default drive strength of 10 mA 5
SDATA delay from BCLK output falling edge tSOD 11.71 ns IOVDD = 3.3 V ± 10%, drive strength set to 0b00, with 25 pF load 5
SDATA delay from BCLK output falling edge tSOD 10.37 ns IOVDD = 3.3 V ± 10%, drive strength set to 0b01, with 25 pF load 5
SDATA delay from BCLK output falling edge tSOD 9.03 ns IOVDD = 3.3 V ± 10%, drive strength set to 0b10, with 25 pF load 5
SDATA delay from BCLK output falling edge tSOD 8.72 ns IOVDD = 3.3 V ± 10%, drive strength set to 0b11, with 25 pF load 5
SDATA delay from BCLK output falling edge tSOD 31.02 ns IOVDD = 1.7 V to 1.89 V, drive strength set to 0b00, with 25 pF load 5
SDATA delay from BCLK output falling edge tSOD 25.83 ns IOVDD = 1.7 V to 1.89 V, drive strength set to 0b01, with 25 pF load 5
SDATA delay from BCLK output falling edge tSOD 20.33 ns IOVDD = 1.7 V to 1.89 V, drive strength set to 0b11, with 25 pF load 5
SCL clock frequency fSCL 1000 kHz 6
SCL pulse width high tSCLH 0.26 µs 6
SCL pulse width low tSCLL 0.5 µs 6
Start and repeated start condition setup time tSCS 0.26 µs 6
Start condition hold time tSCH 0.26 µs 6
Data setup time tDS 50 ns 6
Data hold time tDH 0.45 µs 6
SDA rise time tSDR 120 ns 6
SDA fall time tSDF 120 ns 6
Bus-free time between stop and start tBFT 0.5 µs 6
Stop condition setup time tSUSTO 0.26 µs 6
Data setup time (PDM) tSETUP 9 ns PDM data latched on both edges of the clock 6
Data hold time (PDM) tHOLD 3 ns PDM data latched on both edges of the clock 6
DVDD to Ground 1.98 V 7
IOVDD to Ground 3.63 V 7
Junction Temperature Range -65 165 °C 7
Storage Temperature Range -65 150 °C 7
Soldering temperature 300 °C 60 sec 7
Electrostatic Discharge (ESD) Susceptibility 4.5 kV Test model not stated 7
Thermal resistance, junction-to-ambient θJA 57 °C/W Package CP-16-22; JEDEC 1S0P thermal test board (table footnote 1) 7
Thermal resistance, junction-to-case θJC 15 °C/W Package CP-16-22; JEDEC 2S2P thermal test board with four thermal vias (table footnote 2) 7

CAD (KiCad official)

  • Symbol: ADAU7118ACPZRL
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: LFCSP-16(3x3) (KiCad packages3D, STEP)
  • 3D model files: adau7118acpzrl-etched.step / adau7118acpzrl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); adau7118acpzrl.step / adau7118acpzrl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (35 pp, sha256 8b720e57686f67dd, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF