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AD9838BCPZ-RL7

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Analog Devices Direct Digital Synthesis (DDS), LFCSP-20(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentadc-dac-data conversionad9838bcpz-rl7factory-2.0.0extractor-text

Verified AD9838BCPZ-RL7

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 21 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9838BCPZ-RL7 · LFCSP-20(4x4) · 21 pins
  • ✓copper: 21 copper pads, none touching another net
  • ✓datasheet: all 21 pin names found in the 32-page datasheet
  • ✓distributor: lcsc C653891, digikey 505-AD9838BCPZ-RL7TR-ND, mouser 584-AD9838BCPZ-R7
  • ✓family: QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-pbp5ly7r/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.30)
  • ✓pads: 21 pins = 21 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 21 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9838bcpz-rl7.kicad_sym✓ ad9838bcpz-rl7.kicad_mod✓ ad9838bcpz-rl7.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers ad9838bcpz-rl7: viewers · Ray 2d ago
ad9838bcpz-rl7-etched.glb Publish 0.1.0 · Ray 2d ago
ad9838bcpz-rl7-etched.step ad9838bcpz-rl7: factory component page (tier=mfr) · Ray 2d ago
ad9838bcpz-rl7-hero.glb ad9838bcpz-rl7: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
ad9838bcpz-rl7-hero.overlay.json Publish 0.1.0 · Ray 2d ago
ad9838bcpz-rl7.glb Publish 0.1.0 · Ray 2d ago
ad9838bcpz-rl7.kicad_mod Publish 0.1.0 · Ray 2d ago
ad9838bcpz-rl7.kicad_sym Publish 0.1.0 · Ray 2d ago
ad9838bcpz-rl7.lbr Publish 0.1.0 · Ray 2d ago
ad9838bcpz-rl7.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier mfr, 21 pins · Ray 2d ago

AD9838BCPZ-RL7

Analog Devices · Direct Digital Synthesis (DDS) · LFCSP-20(4x4)

AD9838BCPZ-RL7 from Analog Devices, in a LFCSP-20(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 AVDD power_in Positive power supply for the analog section, 2.3 V to 5.5 V, with a 0.1 µF decoupling capacitor to AGND.
2 DVDD power_in Positive power supply for the digital section, 2.3 V to 5.5 V, with a 0.1 µF decoupling capacitor to DGND.
3 CAP/2.5V passive 2.5 V regulator output generated from DVDD when DVDD exceeds 2.7 V, needs a 100 nF typical capacitor to DGND; short to DVDD if DVDD is 2.7 V or less.
4 DGND power_in Digital ground.
5 MCLK input Digital clock input that sets the DDS output frequency reference, accuracy and phase noise.
6 FSELECT input Frequency select input choosing FREQ0 or FREQ1 for the phase accumulator; tie to CMOS high or low when the FSEL bit is used.
7 PSELECT input Phase select input choosing PHASE0 or PHASE1 to add to the phase accumulator output; tie to CMOS high or low when the PSEL bit is used.
8 RESET input Active-high digital input that resets the internal registers to 0 (midscale analog output) without affecting addressable registers.
9 SLEEP input Active-high digital input that powers down the DAC when high, same function as the SLEEP12 control bit.
10 SDATA input Serial data input for the 16-bit serial data word.
11 SCLK input Serial clock input; data is clocked in on each falling edge of SCLK.
12 FSYNC input Active-low frame synchronization control input; taking it low indicates a new word is being loaded.
13 SIGN BIT OUT output Logic output providing the comparator output or the NCO MSB, enabled by the OPBITEN bit and selected by the SIGN/PIB bit.
14 VIN power_in Comparator input used to generate a square wave from the filtered sinusoidal DAC output.
15 AGND power_in Analog ground.
16 IOUT output High-impedance current output; connect a nominal 200 Ω load resistor to AGND, with a 20 pF capacitor to AGND recommended.
17 IOUTB output Complementary current output; tie to AGND through a 200 Ω load resistor or directly to AGND.
18 FSADJUST passive Full-scale adjust; RSET (6.8 kΩ typical) to AGND sets full-scale current via IOUT FULL SCALE = 18 × FSADJUST/RSET, FSADJUST = 1.14 V nominal.
19 REFOUT output Voltage reference output of the internal 1.20 V reference.
20 COMP passive DAC bias pin used for decoupling the DAC bias voltage.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-20(4x4)
Category ADC/DAC/Data Conversion
Pins 21

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Internal Reference 1.11 1.18 1.24 V 3
Input High Voltage 2.3-2.7 V supply VINH 1.7 V 2.3 V to 2.7 V power supply 4
Input High Voltage 2.7-3.6 V supply VINH 2 V 2.7 V to 3.6 V power supply 4
Input High Voltage 4.5-5.5 V supply VINH 2.8 V 4.5 V to 5.5 V power supply 4
Input Low Voltage 2.3-2.7 V supply VINL 0.6 V 2.3 V to 2.7 V power supply 4
Input Low Voltage 2.7-3.6 V supply VINL 0.7 V 2.7 V to 3.6 V power supply 4
Input Low Voltage 4.5-5.5 V supply VINL 0.8 V 4.5 V to 5.5 V power supply 4
Input Current IINH/IINL 10 µA 4
AVDD supply voltage AVDD 2.3 5.5 V fMCLK = 16 MHz, fOUT = fMCLK/4096 4
DVDD supply voltage DVDD 2.3 5.5 V 4
Analog supply current IAA 3.7 5 mA Digital inputs static, equal to 0 V or DVDD 4
Digital supply current, B Grade IDD 1.2 2.4 mA IDD code dependent; see Figure 7 4
Total supply current, B Grade IAA + IDD 4.9 7.4 mA See Figure 6 4
MCLK period t1 62.5 ns 16 MHz (B grade) 5
MCLK high duration t2 26 ns 16 MHz (B grade) 5
MCLK low duration t3 26 ns 16 MHz (B grade) 5
SCLK period t4 25 ns 5
SCLK high duration t5 10 ns 5
SCLK low duration t6 10 ns 5
FSYNC to SCLK falling edge setup time t7 5 ns 5
SCLK falling edge to FSYNC rising edge time t8 10 ns 5
Data setup time t9 5 ns 5
Data hold time t10 3 ns 5
FSELECT, PSELECT setup time before MCLK rising edge t11 8 ns 5
FSELECT, PSELECT setup time after MCLK rising edge t11A 8 ns 5
SCLK high to FSYNC falling edge setup time t12 5 ns 5
AVDD to AGND AVDD -0.3 6 V TA = 25°C 6
DVDD to DGND DVDD -0.3 6 V TA = 25°C 6
AVDD to DVDD -0.3 0.3 V TA = 25°C 6
AGND to DGND -0.3 0.3 V TA = 25°C 6
CAP/2.5V 2.75 V TA = 25°C 6
Operating Temperature Range (B Version) -40 125 °C Industrial 6
Storage Temperature Range -65 150 °C 6
Maximum Junction Temperature 150 °C 6
Update Rate, B Grade 16 MSPS 3
Output Compliance 0.8 V Guaranteed by design 3
Resolution 10 Bits 3
IOUT Full Scale 3 mA 3
VOUT Maximum 0.6 V 3
VOUT Minimum 30 mV 3
Integral Nonlinearity INL 1 LSB ±1 LSB as printed 3
Differential Nonlinearity DNL 0.5 LSB ±0.5 LSB as printed 3
SNR, B Grade SNR -64 dB fMCLK = 16 MHz, fOUT = fMCLK/4096 3
THD, B Grade THD -64 dBc fMCLK = 16 MHz, fOUT = fMCLK/4096 3
Wideband SFDR, B Grade SFDR -66 dBc fMCLK = 16 MHz, fOUT = fMCLK/50 3
Narrow-Band SFDR, B Grade SFDR -92 dBc fMCLK = 16 MHz, fOUT = fMCLK/50 3
Clock Feedthrough, B Grade -65 dBc fMCLK = 16 MHz, fOUT = reset 3
Wake-Up Time 1 ms 3
Comparator Input Voltage Range 1 V p-p AC-coupled internally 3
Comparator Input Capacitance 10 pF 3
Comparator Input Leakage Current 10 µA 3
Output Rise/Fall Time 12 ns Using a 15 pF load 3
Reference TC 100 ppm/°C 3
FSADJUST Voltage 1.14 V 3
Input Capacitance CIN 3 pF 4
Low Power Sleep Mode current, B Grade 0.4 mA DAC powered down; see Table 17 4
Thermal resistance junction-to-ambient θJA 49.5 °C/W 20-Lead LFCSP_WQ (CP-20-10) 6
Thermal resistance junction-to-case θJC 5.3 °C/W 20-Lead LFCSP_WQ (CP-20-10) 6

CAD (KiCad official)

  • Symbol: AD9838BCPZ-RL7
  • Footprint: Package_DFN_QFN:QFN-20-1EP_4x4mm_P0.5mm_EP2.5x2.5mm
  • 3D model: LFCSP-20(4x4) (KiCad packages3D, STEP)
  • 3D model files: ad9838bcpz-rl7-etched.step / ad9838bcpz-rl7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9838bcpz-rl7.step / ad9838bcpz-rl7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (32 pp, sha256 fd7a8033e90ea2cb, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF