AD9832BRUZ-REEL

{
  "schema_version": 1,
  "type": "component",
  "slug": "ad9832bruz-reel",
  "title": "AD9832BRUZ-REEL",
  "brief": "Analog Devices Direct Digital Synthesis (DDS), TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
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    "data converters",
    "ad9832bruz-reel",
    "factory-2.0.0",
    "extractor-text"
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  "component": {
    "mpn": "AD9832BRUZ-REEL",
    "manufacturer": "Analog Devices",
    "package": "TSSOP-16",
    "pin_count": 16,
    "category": "Data Converters",
    "subcategory": "Direct Digital Synthesis (DDS)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9832.pdf",
    "parts": {
      "symbol": "ad9832bruz-reel.kicad_sym",
      "footprint": "ad9832bruz-reel.kicad_mod",
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      "lbr": "ad9832bruz-reel.lbr"
    },
    "distributor_links": {
      "lcsc": "C26333",
      "digikey": "505-AD9832BRUZ-REELTR-ND",
      "mouser": "584-AD9832BRUZ-R"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T22:27:19Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD9832BRUZ-REELTR-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD9832BRUZ-R",
        "status": "found",
        "lifecycle": "Restricted Availability"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "FS ADJUST",
        "type": "passive",
        "description": "Full-scale adjust control: a resistor RSET (3.9 kΩ typical) connects between this pin and AGND to set the full-scale DAC current, IOUTFULL-SCALE = 12.5 × VREFIN/RSET with VREFIN = 1.21 V nominal."
      },
      {
        "number": "2",
        "name": "REFIN",
        "type": "input",
        "description": "Voltage reference input that accepts a 1.21 V nominal reference, either the on-board reference from REFOUT or an external one."
      },
      {
        "number": "3",
        "name": "REFOUT",
        "type": "output",
        "description": "Voltage reference output of 1.21 V nominal, connected to REFIN to use it as the DAC reference and decoupled with a 10 nF capacitor to AGND."
      },
      {
        "number": "4",
        "name": "DVDD",
        "type": "power_in",
        "description": "Positive power supply for the digital section, decoupled with 0.1 µF to DGND, specified as 5 V ± 10% or 3.3 V ± 0%."
      },
      {
        "number": "5",
        "name": "DGND",
        "type": "power_in",
        "description": "Digital ground."
      },
      {
        "number": "6",
        "name": "MCLK",
        "type": "input",
        "description": "Digital clock input, up to 25 MHz, with DDS output frequencies expressed as a binary fraction of MCLK, which determines output frequency accuracy and phase noise."
      },
      {
        "number": "7",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock logic input; data is clocked into the device on each falling SCLK edge."
      },
      {
        "number": "8",
        "name": "SDATA",
        "type": "input",
        "description": "Serial data logic input to which the 16-bit serial data word is applied."
      },
      {
        "number": "9",
        "name": "FSYNC",
        "type": "input",
        "description": "Data synchronization logic input; a low level tells the internal logic that a new word is being loaded."
      },
      {
        "number": "10",
        "name": "FSELECT",
        "type": "input",
        "description": "Frequency select input choosing FREQ0 or FREQ1 for the phase accumulator, sampled on the rising MCLK edge, and tied to DGND when the FSELECT bit is used instead."
      },
      {
        "number": "11",
        "name": "PSEL1",
        "type": "input",
        "description": "Phase select input (with PSEL0) choosing one of four phase registers, sampled on the rising MCLK edge, and tied to DGND when the PSEL bits are used instead."
      },
      {
        "number": "12",
        "name": "PSEL0",
        "type": "input",
        "description": "Phase select input (with PSEL1) choosing one of four phase registers, sampled on the rising MCLK edge, and tied to DGND when the PSEL bits are used instead."
      },
      {
        "number": "13",
        "name": "AGND",
        "type": "power_in",
        "description": "Analog ground."
      },
      {
        "number": "14",
        "name": "IOUT",
        "type": "output",
        "description": "High-impedance current source output, with a load resistor connected between IOUT and AGND."
      },
      {
        "number": "15",
        "name": "AVDD",
        "type": "power_in",
        "description": "Positive power supply for the analog section, decoupled with 0.1 µF to AGND, specified as 5 V ± 10% or 3.3 V ± 10%."
      },
      {
        "number": "16",
        "name": "COMP",
        "type": "passive",
        "description": "Compensation pin for the internal reference amplifier, with a 10 nF ceramic decoupling capacitor connected between COMP and AVDD."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-sonnet-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Table 4 lists '11, 12' as 'PSEL1, PSEL0'; the figure text extraction is jumbled, so the order was ta; The datasheet gives DVDD as '3.3 V ± 0%' (likely a typo) and the specification table gives 2.97/5.5 "
        ],
        "pages_sent": 13,
        "cost_usd": 0.0902,
        "at": "2026-10-30T22:27:08"
      },
      "datasheet": {
        "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9832.pdf",
        "pages": 28,
        "sha256": "effe0e8501ec1bc2",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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        "seat": "z = 0",
        "extents_mm": [
          6.4,
          5,
          1.1
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
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    ],
    "package_dims": {
      "package_code": "RU-16",
      "source_page": 26,
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        "nom_mm": 5,
        "range_mm": [
          4.9,
          5.1
        ]
      },
      "E1": {
        "nom_mm": 4.4,
        "range_mm": [
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        ]
      },
      "E": {
        "nom_mm": 6.4,
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      },
      "e": {
        "nom_mm": 0.65,
        "range_mm": [
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          null
        ]
      },
      "A": {
        "nom_mm": 1.2,
        "range_mm": [
          null,
          1.2
        ]
      },
      "source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
      "model_check": {
        "file": "ad9832bruz-reel.step",
        "verdict": "PASS",
        "reasons": [
          "height and body within the datasheet's package drawing"
        ],
        "by": "factory/package_fit.py"
      }
    }
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "TSSOP-16",
      "Category": "Data Converters",
      "Pins": "16"
    }
  },
  "variants": [],
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    "ad9832bruz-reel"
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  "discovery_pitch": "AD9832BRUZ-REEL (Analog Devices) component page: datasheet pinout, KiCad symbol, footprint and 3D.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
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