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AD9832BRUZ-REEL

Analog Devices · Direct Digital Synthesis (DDS) · TSSOP-16

AD9832BRUZ-REEL from Analog Devices, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FS ADJUST passive Full-scale adjust control: a resistor RSET (3.9 kΩ typical) connects between this pin and AGND to set the full-scale DAC current, IOUTFULL-SCALE = 12.5 × VREFIN/RSET with VREFIN = 1.21 V nominal.
2 REFIN input Voltage reference input that accepts a 1.21 V nominal reference, either the on-board reference from REFOUT or an external one.
3 REFOUT output Voltage reference output of 1.21 V nominal, connected to REFIN to use it as the DAC reference and decoupled with a 10 nF capacitor to AGND.
4 DVDD power_in Positive power supply for the digital section, decoupled with 0.1 µF to DGND, specified as 5 V ± 10% or 3.3 V ± 0%.
5 DGND power_in Digital ground.
6 MCLK input Digital clock input, up to 25 MHz, with DDS output frequencies expressed as a binary fraction of MCLK, which determines output frequency accuracy and phase noise.
7 SCLK input Serial clock logic input; data is clocked into the device on each falling SCLK edge.
8 SDATA input Serial data logic input to which the 16-bit serial data word is applied.
9 FSYNC input Data synchronization logic input; a low level tells the internal logic that a new word is being loaded.
10 FSELECT input Frequency select input choosing FREQ0 or FREQ1 for the phase accumulator, sampled on the rising MCLK edge, and tied to DGND when the FSELECT bit is used instead.
11 PSEL1 input Phase select input (with PSEL0) choosing one of four phase registers, sampled on the rising MCLK edge, and tied to DGND when the PSEL bits are used instead.
12 PSEL0 input Phase select input (with PSEL1) choosing one of four phase registers, sampled on the rising MCLK edge, and tied to DGND when the PSEL bits are used instead.
13 AGND power_in Analog ground.
14 IOUT output High-impedance current source output, with a load resistor connected between IOUT and AGND.
15 AVDD power_in Positive power supply for the analog section, decoupled with 0.1 µF to AGND, specified as 5 V ± 10% or 3.3 V ± 10%.
16 COMP passive Compensation pin for the internal reference amplifier, with a 10 nF ceramic decoupling capacitor connected between COMP and AVDD.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package TSSOP-16
Category Data Converters
Pins 16

CAD (KiCad official)

  • Symbol: AD9832BRUZ-REEL
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: ad9832bruz-reel-etched.step / ad9832bruz-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9832bruz-reel.step / ad9832bruz-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (28 pp, sha256 effe0e8501ec1bc2, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF