main
Ray Publish 0.1.0 3009d53 3d ago
{
  "slug": "ad9742acpz",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Digital To Analog Converters (DACs), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "adc-dac-data conversion",
    "ad9742acpz",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "ad9742acpz.kicad_sym",
    "ad9742acpz.kicad_mod",
    "ad9742acpz.glb",
    "ad9742acpz.step",
    "ad9742acpz.lbr",
    "docs/hero.png",
    "docs/ad9742acpz-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ad9742acpz-hero.glb",
    "ad9742acpz-hero.overlay.json",
    "ad9742acpz-etched.glb"
  ],
  "component": {
    "mpn": "AD9742ACPZ",
    "manufacturer": "Analog Devices",
    "package": "LFCSP-32(5x5)",
    "pin_count": 33,
    "category": "ADC/DAC/Data Conversion",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9742.pdf",
    "parts": {
      "symbol": "ad9742acpz.kicad_sym",
      "footprint": "ad9742acpz.kicad_mod",
      "model_3d": "ad9742acpz-hero.glb",
      "model_3d_plain": "ad9742acpz-etched.glb",
      "model_3d_step": "ad9742acpz-etched.step",
      "model_3d_step_plain": "ad9742acpz.step",
      "lbr": "ad9742acpz.lbr"
    },
    "distributor_links": {
      "lcsc": "C578868",
      "digikey": "505-AD9742ACPZ-ND",
      "mouser": "584-AD9742ACPZ"
    },
    "distributor_check": {
      "checked_at": "2026-10-30T22:40:58Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD9742ACPZ-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD9742ACPZ",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "DB5",
        "type": "input",
        "description": "Data bit 5 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "2",
        "name": "DB4",
        "type": "input",
        "description": "Data bit 4 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "3",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital supply voltage of 3.3 V nominal, with a 2.7 V to 3.6 V supply range."
      },
      {
        "number": "4",
        "name": "DB3",
        "type": "input",
        "description": "Data bit 3 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "5",
        "name": "DB2",
        "type": "input",
        "description": "Data bit 2 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "6",
        "name": "DB1",
        "type": "input",
        "description": "Data bit 1 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "7",
        "name": "DB0",
        "type": "input",
        "description": "Least significant data bit (LSB) input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "8",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection."
      },
      {
        "number": "9",
        "name": "NC",
        "type": "unconnected",
        "description": "No internal connection."
      },
      {
        "number": "10",
        "name": "DCOM",
        "type": "power_in",
        "description": "Digital common ground for the digital supply DVDD."
      },
      {
        "number": "11",
        "name": "CLKVDD",
        "type": "power_in",
        "description": "Clock supply voltage of 3.3 V nominal, with a 2.7 V to 3.6 V supply range."
      },
      {
        "number": "12",
        "name": "CLK+",
        "type": "input",
        "description": "Differential clock input; in differential mode the common-mode level can vary from 0.75 V to 2.25 V with differential swing as low as 0.5 V p-p, and in single-ended mode it is driven rail-to-rail."
      },
      {
        "number": "13",
        "name": "CLK−",
        "type": "input",
        "description": "Complementary differential clock input, which is left floating in single-ended clock mode."
      },
      {
        "number": "14",
        "name": "CLKCOM",
        "type": "power_in",
        "description": "Clock common ground; connecting CMODE to this pin selects the single-ended clock receiver."
      },
      {
        "number": "15",
        "name": "CMODE",
        "type": "input",
        "description": "Clock mode select: connect to CLKCOM for single-ended, to CLKVDD for differential, or float for PECL receiver mode."
      },
      {
        "number": "16",
        "name": "MODE",
        "type": "input",
        "description": "Input data format select: connect to DCOM for straight binary coding or to DVDD for twos complement coding."
      },
      {
        "number": "17",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog supply voltage of 3.3 V nominal, with a 2.7 V to 3.6 V supply range."
      },
      {
        "number": "18",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog supply voltage of 3.3 V nominal, with a 2.7 V to 3.6 V supply range."
      },
      {
        "number": "19",
        "name": "ACOM",
        "type": "power_in",
        "description": "Analog common ground for the analog supply AVDD."
      },
      {
        "number": "20",
        "name": "IOUTB",
        "type": "output",
        "description": "Complementary DAC current output carrying full-scale current when all data bits are 0, with output compliance range of -1 V to +1.25 V."
      },
      {
        "number": "21",
        "name": "IOUTA",
        "type": "output",
        "description": "DAC current output carrying full-scale current when all data bits are 1, with output compliance range of -1 V to +1.25 V."
      },
      {
        "number": "22",
        "name": "ACOM",
        "type": "power_in",
        "description": "Analog common ground for the analog supply AVDD."
      },
      {
        "number": "23",
        "name": "REFIO",
        "type": "bidirectional",
        "description": "Reference input/output that requires a 0.1 µF capacitor to ACOM when the internal 1.2 V reference is active."
      },
      {
        "number": "24",
        "name": "FS ADJ",
        "type": "passive",
        "description": "Full-scale current output adjust pin that sets the DAC full-scale output current."
      },
      {
        "number": "25",
        "name": "SLEEP",
        "type": "input",
        "description": "Active-high power-down control input with an active pull-down circuit, which may be left unterminated if not used."
      },
      {
        "number": "26",
        "name": "DCOM",
        "type": "power_in",
        "description": "Digital common ground for the digital supply DVDD."
      },
      {
        "number": "27",
        "name": "DB11",
        "type": "input",
        "description": "Most significant data bit (MSB) input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "28",
        "name": "DB10",
        "type": "input",
        "description": "Data bit 10 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "29",
        "name": "DB9",
        "type": "input",
        "description": "Data bit 9 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "30",
        "name": "DB8",
        "type": "input",
        "description": "Data bit 8 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "31",
        "name": "DB7",
        "type": "input",
        "description": "Data bit 7 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "32",
        "name": "DB6",
        "type": "input",
        "description": "Data bit 6 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families."
      },
      {
        "number": "33",
        "name": "EP",
        "type": "passive",
        "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The exposed pad (EPAD) is not a numbered pin in Table 6 and is omitted from the pins list. Table 6 r"
        ],
        "pages_sent": 10,
        "cost_usd": 0.0273,
        "at": "2026-10-30T22:40:48"
      },
      "datasheet": {
        "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9742.pdf",
        "pages": 32,
        "sha256": "ea3ba19811fe66fd",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 33,
        "described": 33,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
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      "footprint": "viewers/footprint.html"
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
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        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "5fa713ea46b36980895812ed853577889b7cb06d275041a39b99bc0be305dc79",
        "checked": "2026-10-30",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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      {
        "file": "ad9742acpz-etched.step",
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        "sha256": "aa17686c2a1de6cd1030161a3733dcad9a114015e9a9fbbc2093f8fd7e96ae68",
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        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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  }
}