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AD9742ACPZ
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Analog Devices Digital To Analog Converters (DACs), LFCSP-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownAD9742ACPZ
Analog Devices · Digital To Analog Converters (DACs) · LFCSP-32(5x5)
AD9742ACPZ from Analog Devices, in a LFCSP-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DB5 | input | Data bit 5 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 2 | DB4 | input | Data bit 4 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 3 | DVDD | power_in | Digital supply voltage of 3.3 V nominal, with a 2.7 V to 3.6 V supply range. |
| 4 | DB3 | input | Data bit 3 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 5 | DB2 | input | Data bit 2 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 6 | DB1 | input | Data bit 1 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 7 | DB0 | input | Least significant data bit (LSB) input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 8 | NC | unconnected | No internal connection. |
| 9 | NC | unconnected | No internal connection. |
| 10 | DCOM | power_in | Digital common ground for the digital supply DVDD. |
| 11 | CLKVDD | power_in | Clock supply voltage of 3.3 V nominal, with a 2.7 V to 3.6 V supply range. |
| 12 | CLK+ | input | Differential clock input; in differential mode the common-mode level can vary from 0.75 V to 2.25 V with differential swing as low as 0.5 V p-p, and in single-ended mode it is driven rail-to-rail. |
| 13 | CLK− | input | Complementary differential clock input, which is left floating in single-ended clock mode. |
| 14 | CLKCOM | power_in | Clock common ground; connecting CMODE to this pin selects the single-ended clock receiver. |
| 15 | CMODE | input | Clock mode select: connect to CLKCOM for single-ended, to CLKVDD for differential, or float for PECL receiver mode. |
| 16 | MODE | input | Input data format select: connect to DCOM for straight binary coding or to DVDD for twos complement coding. |
| 17 | AVDD | power_in | Analog supply voltage of 3.3 V nominal, with a 2.7 V to 3.6 V supply range. |
| 18 | AVDD | power_in | Analog supply voltage of 3.3 V nominal, with a 2.7 V to 3.6 V supply range. |
| 19 | ACOM | power_in | Analog common ground for the analog supply AVDD. |
| 20 | IOUTB | output | Complementary DAC current output carrying full-scale current when all data bits are 0, with output compliance range of -1 V to +1.25 V. |
| 21 | IOUTA | output | DAC current output carrying full-scale current when all data bits are 1, with output compliance range of -1 V to +1.25 V. |
| 22 | ACOM | power_in | Analog common ground for the analog supply AVDD. |
| 23 | REFIO | bidirectional | Reference input/output that requires a 0.1 µF capacitor to ACOM when the internal 1.2 V reference is active. |
| 24 | FS ADJ | passive | Full-scale current output adjust pin that sets the DAC full-scale output current. |
| 25 | SLEEP | input | Active-high power-down control input with an active pull-down circuit, which may be left unterminated if not used. |
| 26 | DCOM | power_in | Digital common ground for the digital supply DVDD. |
| 27 | DB11 | input | Most significant data bit (MSB) input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 28 | DB10 | input | Data bit 10 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 29 | DB9 | input | Data bit 9 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 30 | DB8 | input | Data bit 8 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 31 | DB7 | input | Data bit 7 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 32 | DB6 | input | Data bit 6 input of the 12-bit parallel data bus, with digital inputs supporting 3 V CMOS logic families. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | LFCSP-32(5x5) |
| Category | ADC/DAC/Data Conversion |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Integral Linearity Error | INL | -2.5 | 0.5 | 2.5 | LSB | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 |
| Differential Nonlinearity | DNL | -1.3 | 0.4 | 1.3 | LSB | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 |
| Offset Error | -0.02 | 0.02 | % of FSR | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 | ||
| Gain Error (Without Internal Reference) | -0.5 | 0.1 | 0.5 | % of FSR | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 | |
| Gain Error (With Internal Reference) | -0.5 | 0.1 | 0.5 | % of FSR | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 | |
| Full-Scale Output Current | IOUTFS | 2 | 20 | mA | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 | |
| Output Compliance Range | -1 | 1.25 | V | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 | ||
| Reference Voltage | 1.14 | 1.2 | 1.26 | V | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 | |
| Reference Input Compliance Range | 0.1 | 1.25 | V | TMIN to TMAX, AVDD=DVDD=CLKVDD=3.3 V, IOUTFS=20 mA | 3 | ||
| Gain Drift (Without Internal Reference) | -50 | 50 | ppm of FSR/°C | 3 | |||
| Gain Drift (With Internal Reference) | -100 | 100 | ppm of FSR/°C | 3 | |||
| Reference Voltage Drift | -50 | 50 | ppm/°C | 3 | |||
| Offset Drift | 0 | ppm of FSR/°C | 3 | ||||
| Supply Voltage AVDD | AVDD | 2.7 | 3.3 | 3.6 | V | 3 | |
| Supply Voltage DVDD | DVDD | 2.7 | 3.3 | 3.6 | V | 3 | |
| Supply Voltage CLKVDD | CLKVDD | 2.7 | 3.3 | 3.6 | V | 3 | |
| Operating Range | -40 | 85 | °C | 3 | |||
| Power Supply Rejection Ratio, AVDD | -1 | 1 | % of FSR/V | ±5% power supply variation | 3 | ||
| Power Supply Rejection Ratio, DVDD | -0.04 | 0.04 | % of FSR/V | ±5% power supply variation | 3 | ||
| Maximum Output Update Rate | fCLOCK | 210 | MSPS | 4 | |||
| Logic 1 Current | -10 | 10 | µA | Digital inputs, TMIN to TMAX, DVDD=3.3 V | 5 | ||
| Logic 0 Current | -10 | 10 | µA | Digital inputs, TMIN to TMAX, DVDD=3.3 V | 5 | ||
| Input Setup Time | tS | 2 | ns | 5 | |||
| Input Hold Time | tH | 1.5 | ns | 5 | |||
| Latch Pulse Width | tLPW | 1.5 | ns | 5 | |||
| Clock Input Voltage Range | 0 | 3 | V | CLK inputs in differential or PECL mode | 5 | ||
| Clock Common-Mode Voltage | 0.75 | 1.5 | 2.25 | V | Applicable to CLK+ and CLK− when configured for differential or PECL clock input mode | 5 | |
| Clock Differential Voltage | 0.5 | V | Applicable to CLK+ and CLK− when configured for differential or PECL clock input mode | 5 | |||
| AVDD to ACOM | AVDD | -0.3 | 3.9 | V | With respect to ACOM | 6 | |
| DVDD to DCOM | DVDD | -0.3 | 3.9 | V | With respect to DCOM | 6 | |
| CLKVDD to CLKCOM | CLKVDD | -0.3 | 3.9 | V | With respect to CLKCOM | 6 | |
| ACOM to DCOM | -0.3 | 0.3 | V | 6 | |||
| ACOM to CLKCOM | -0.3 | 0.3 | V | 6 | |||
| DCOM to CLKCOM | -0.3 | 0.3 | V | 6 | |||
| AVDD to DVDD | AVDD | -3.9 | 3.9 | V | 6 | ||
| AVDD to CLKVDD | AVDD | -3.9 | 3.9 | V | 6 | ||
| DVDD to CLKVDD | DVDD | -3.9 | 3.9 | V | 6 | ||
| CLOCK, SLEEP Input Voltage | -0.3 | V | With respect to DCOM; upper limit printed as DVDD + 0.3 | 6 | |||
| Digital Inputs MODE Voltage | -0.3 | V | With respect to DCOM; upper limit printed as DVDD + 0.3 | 6 | |||
| IOUTA, IOUTB Voltage | -1 | V | With respect to ACOM; upper limit printed as AVDD + 0.3 | 6 | |||
| REFIO, REFLO, FS ADJ Voltage | -0.3 | V | With respect to ACOM; upper limit printed as AVDD + 0.3 | 6 | |||
| CLK+, CLK−, MODE Voltage | -0.3 | V | With respect to CLKCOM; upper limit printed as CLKVDD + 0.3 | 6 | |||
| Junction Temperature | 150 | °C | 6 | ||||
| Storage Temperature | -65 | 150 | °C | 6 | |||
| Lead Temperature | 300 | °C | 10 sec | 6 | |||
| Thermal Resistance θJA | θJA | 32.5 | °C/W | 32-Lead LFCSP, 4-layer board in still air, EIA/JESD51-7 | 6 |
CAD (KiCad official)
- Symbol:
AD9742ACPZ - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: LFCSP-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
ad9742acpz-etched.step/ad9742acpz-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad9742acpz.step/ad9742acpz.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (32 pp, sha256
ea3ba19811fe66fd, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).