AD9717BCPZ

{
  "slug": "ad9717bcpz",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Digital To Analog Converters (DACs), LFCSP-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "data converters",
    "ad9717bcpz",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "ad9717bcpz.kicad_sym",
    "ad9717bcpz.kicad_mod",
    "ad9717bcpz.glb",
    "ad9717bcpz.step",
    "ad9717bcpz.lbr",
    "docs/hero.png",
    "docs/ad9717bcpz-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "ad9717bcpz-hero.glb",
    "ad9717bcpz-hero.overlay.json",
    "ad9717bcpz-etched.glb"
  ],
  "component": {
    "mpn": "AD9717BCPZ",
    "manufacturer": "Analog Devices",
    "package": "LFCSP-40(6x6)",
    "pin_count": 41,
    "category": "Data Converters",
    "subcategory": "Digital To Analog Converters (DACs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9714_9715_9716_9717.pdf",
    "parts": {
      "symbol": "ad9717bcpz.kicad_sym",
      "footprint": "ad9717bcpz.kicad_mod",
      "model_3d": "ad9717bcpz-hero.glb",
      "model_3d_plain": "ad9717bcpz-etched.glb",
      "model_3d_step": "ad9717bcpz-etched.step",
      "model_3d_step_plain": "ad9717bcpz.step",
      "lbr": "ad9717bcpz.lbr"
    },
    "distributor_links": {
      "lcsc": "C578865",
      "digikey": "505-AD9717BCPZ-ND",
      "mouser": "584-AD9717BCPZ"
    },
    "distributor_check": {
      "checked_at": "2026-10-28T22:58:44Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "505-AD9717BCPZ-ND",
        "status": "found"
      },
      "mouser": {
        "pn": "584-AD9717BCPZ",
        "status": "found"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "DB11",
        "type": "input",
        "description": "Digital data input bit DB11 (MSB group DB[11:8]); absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "2",
        "name": "DB10",
        "type": "input",
        "description": "Digital data input bit DB10; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "3",
        "name": "DB9",
        "type": "input",
        "description": "Digital data input bit DB9; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "4",
        "name": "DB8",
        "type": "input",
        "description": "Digital data input bit DB8; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "5",
        "name": "DVDDIO",
        "type": "power_in",
        "description": "Digital I/O supply voltage, 1.8 V to 3.3 V nominal."
      },
      {
        "number": "6",
        "name": "DVSS",
        "type": "power_in",
        "description": "Digital common; AVSS to DVSS is limited to ±0.3 V."
      },
      {
        "number": "7",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital core supply of 1.8 V; strap to DVDDIO if DVDDIO is 1.8 V, otherwise bypass with a 1.0 μF capacitor, and do not connect external loads to it."
      },
      {
        "number": "8",
        "name": "DB7",
        "type": "input",
        "description": "Digital data input bit DB7; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "9",
        "name": "DB6",
        "type": "input",
        "description": "Digital data input bit DB6; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "10",
        "name": "DB5",
        "type": "input",
        "description": "Digital data input bit DB5; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "11",
        "name": "DB4",
        "type": "input",
        "description": "Digital data input bit DB4; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "12",
        "name": "DB3",
        "type": "input",
        "description": "Digital data input bit DB3; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "13",
        "name": "DB2",
        "type": "input",
        "description": "Digital data input bit DB2; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "14",
        "name": "DB1",
        "type": "input",
        "description": "Digital data input bit DB1; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "15",
        "name": "DB0",
        "type": "input",
        "description": "Digital data input LSB DB0; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "16",
        "name": "DCLKIO",
        "type": "bidirectional",
        "description": "Data input/output clock used to qualify the input data."
      },
      {
        "number": "17",
        "name": "CVDD",
        "type": "power_in",
        "description": "Sampling clock supply voltage, 1.8 V to 3.3 V, which must be greater than or equal to DVDD."
      },
      {
        "number": "18",
        "name": "CLKIN",
        "type": "input",
        "description": "Single-ended LVCMOS sampling clock input supporting a 125 MSPS conversion rate."
      },
      {
        "number": "19",
        "name": "CVSS",
        "type": "power_in",
        "description": "Sampling clock supply common; AVSS to CVSS is limited to ±0.3 V."
      },
      {
        "number": "20",
        "name": "CMLQ",
        "type": "passive",
        "description": "Q DAC output common-mode level: leave unconnected when internal QRCML is enabled, otherwise connect to AVSS through an external resistor (recommended 0 Ω)."
      },
      {
        "number": "21",
        "name": "RLQN",
        "type": "passive",
        "description": "500 Ω load resistor to CMLQ; tie to QOUTN externally to use the internal load resistor."
      },
      {
        "number": "22",
        "name": "QOUTN",
        "type": "output",
        "description": "Complementary Q DAC current output that sources full scale when all data bits are 0s; absolute range is −1.0 V to AVDD + 0.3 V relative to AVSS."
      },
      {
        "number": "23",
        "name": "QOUTP",
        "type": "output",
        "description": "Q DAC current output that sources full scale when all data bits are 1s; absolute range is −1.0 V to AVDD + 0.3 V relative to AVSS."
      },
      {
        "number": "24",
        "name": "RLQP",
        "type": "passive",
        "description": "500 Ω load resistor to CMLQ; tie to QOUTP externally to use the internal load resistor."
      },
      {
        "number": "25",
        "name": "AVSS",
        "type": "power_in",
        "description": "Analog common, which is also the connection for the exposed pad."
      },
      {
        "number": "26",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog supply voltage, 1.8 V to 3.3 V."
      },
      {
        "number": "27",
        "name": "RLIP",
        "type": "passive",
        "description": "500 Ω load resistor to CMLI; tie to IOUTP externally to use the internal load resistor."
      },
      {
        "number": "28",
        "name": "IOUTP",
        "type": "output",
        "description": "I DAC current output that sources full scale when all data bits are 1s; absolute range is −1.0 V to AVDD + 0.3 V relative to AVSS."
      },
      {
        "number": "29",
        "name": "IOUTN",
        "type": "output",
        "description": "Complementary I DAC current output that sources full scale when all data bits are 0s; absolute range is −1.0 V to AVDD + 0.3 V relative to AVSS."
      },
      {
        "number": "30",
        "name": "RLIN",
        "type": "passive",
        "description": "500 Ω load resistor to CMLI; tie to IOUTN externally to use the internal load resistor."
      },
      {
        "number": "31",
        "name": "CMLI",
        "type": "passive",
        "description": "I DAC output common-mode level: leave unconnected when internal IRCML is enabled, otherwise connect to AVSS through an external resistor (recommended 0 Ω)."
      },
      {
        "number": "32",
        "name": "FSADJQ/AUXQ",
        "type": "passive",
        "description": "Full-scale current adjust for Q DAC (nominal 16 kΩ to AVSS for 2 mA output) when internal QRSET is disabled; serves as auxiliary Q DAC output AUXQ when internal QRSET is enabled."
      },
      {
        "number": "33",
        "name": "FSADJI/AUXI",
        "type": "passive",
        "description": "Full-scale current adjust for I DAC (nominal 16 kΩ to AVSS for 2 mA output) when internal IRSET is disabled; serves as auxiliary I DAC output AUXI when internal IRSET is enabled."
      },
      {
        "number": "34",
        "name": "REFIO",
        "type": "bidirectional",
        "description": "Reference input when the internal reference is disabled; provides a 1.0 V reference output in internal mode and requires a 0.1 μF capacitor to AVSS."
      },
      {
        "number": "35",
        "name": "RESET/PINMD",
        "type": "input",
        "description": "Logic low (pull-down to DVSS) selects SPI mode and a logic high pulse of at least 50 ns followed by logic low resets the SPI registers; logic high (pull-up to DVDDIO) selects pin mode."
      },
      {
        "number": "36",
        "name": "SCLK/CLKMD",
        "type": "input",
        "description": "In SPI mode this is the serial clock input with a maximum frequency of 20 MHz; in pin mode it sets the retiming clock phase (tie to 0 when DCLKIO = CLKIN, otherwise pulse 0 to 1)."
      },
      {
        "number": "37",
        "name": "SDIO/FORMAT",
        "type": "bidirectional",
        "description": "In SPI mode this is the bidirectional serial data line; in pin mode a logic low selects binary input format and a logic high (pull-up to DVDDIO) selects two's complement format."
      },
      {
        "number": "38",
        "name": "CS/PWRDN",
        "type": "input",
        "description": "In SPI mode this is the active-low chip select; in pin mode a logic high (pull-up to DVDDIO) powers down the device except the SPI port."
      },
      {
        "number": "39",
        "name": "DB13",
        "type": "input",
        "description": "Digital data input MSB DB13; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "40",
        "name": "DB12",
        "type": "input",
        "description": "Digital data input bit DB12; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS."
      },
      {
        "number": "41",
        "name": "EPAD",
        "type": "power_in",
        "description": "Exposed pad connected to AVSS that should be soldered to the ground plane; exposed metal at the package corners is connected to this pad."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "5/41 pins cited to the wrong page (name found elsewhere): ['4:DB8@p16', '9:DB6@p16', '11:DB4@p16', '12:DB3@p16']"
        ],
        "pages_sent": 17,
        "cost_usd": 0.1209,
        "at": "2026-10-28T22:58:23"
      },
      "datasheet": {
        "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9714_9715_9716_9717.pdf",
        "pages": 54,
        "sha256": "5ea573ba516b2167",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 41,
        "described": 41,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "models_3d": [
      {
        "file": "ad9717bcpz.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          6.0,
          1.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "e5b4286c2329085d9ef7f90d5eb5bf41a435241ecc1baaf1383823b6d6a946ae",
        "checked": "2026-10-28",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "ad9717bcpz-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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          6.0,
          1.0
        ],
        "zmin_mm": 0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "923613facce94fdde0676f425e58ece931e4919da4cf9df5dcde90f446dd5dea",
        "checked": "2026-10-28",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  }
}