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AD9717BCPZ

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Analog Devices Digital To Analog Converters (DACs), LFCSP-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9717BCPZ

Analog Devices · Digital To Analog Converters (DACs) · LFCSP-40(6x6)

AD9717BCPZ from Analog Devices, in a LFCSP-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DB11 input Digital data input bit DB11 (MSB group DB[11:8]); absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
2 DB10 input Digital data input bit DB10; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
3 DB9 input Digital data input bit DB9; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
4 DB8 input Digital data input bit DB8; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
5 DVDDIO power_in Digital I/O supply voltage, 1.8 V to 3.3 V nominal.
6 DVSS power_in Digital common; AVSS to DVSS is limited to ±0.3 V.
7 DVDD power_in Digital core supply of 1.8 V; strap to DVDDIO if DVDDIO is 1.8 V, otherwise bypass with a 1.0 μF capacitor, and do not connect external loads to it.
8 DB7 input Digital data input bit DB7; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
9 DB6 input Digital data input bit DB6; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
10 DB5 input Digital data input bit DB5; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
11 DB4 input Digital data input bit DB4; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
12 DB3 input Digital data input bit DB3; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
13 DB2 input Digital data input bit DB2; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
14 DB1 input Digital data input bit DB1; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
15 DB0 input Digital data input LSB DB0; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
16 DCLKIO bidirectional Data input/output clock used to qualify the input data.
17 CVDD power_in Sampling clock supply voltage, 1.8 V to 3.3 V, which must be greater than or equal to DVDD.
18 CLKIN input Single-ended LVCMOS sampling clock input supporting a 125 MSPS conversion rate.
19 CVSS power_in Sampling clock supply common; AVSS to CVSS is limited to ±0.3 V.
20 CMLQ passive Q DAC output common-mode level: leave unconnected when internal QRCML is enabled, otherwise connect to AVSS through an external resistor (recommended 0 Ω).
21 RLQN passive 500 Ω load resistor to CMLQ; tie to QOUTN externally to use the internal load resistor.
22 QOUTN output Complementary Q DAC current output that sources full scale when all data bits are 0s; absolute range is −1.0 V to AVDD + 0.3 V relative to AVSS.
23 QOUTP output Q DAC current output that sources full scale when all data bits are 1s; absolute range is −1.0 V to AVDD + 0.3 V relative to AVSS.
24 RLQP passive 500 Ω load resistor to CMLQ; tie to QOUTP externally to use the internal load resistor.
25 AVSS power_in Analog common, which is also the connection for the exposed pad.
26 AVDD power_in Analog supply voltage, 1.8 V to 3.3 V.
27 RLIP passive 500 Ω load resistor to CMLI; tie to IOUTP externally to use the internal load resistor.
28 IOUTP output I DAC current output that sources full scale when all data bits are 1s; absolute range is −1.0 V to AVDD + 0.3 V relative to AVSS.
29 IOUTN output Complementary I DAC current output that sources full scale when all data bits are 0s; absolute range is −1.0 V to AVDD + 0.3 V relative to AVSS.
30 RLIN passive 500 Ω load resistor to CMLI; tie to IOUTN externally to use the internal load resistor.
31 CMLI passive I DAC output common-mode level: leave unconnected when internal IRCML is enabled, otherwise connect to AVSS through an external resistor (recommended 0 Ω).
32 FSADJQ/AUXQ passive Full-scale current adjust for Q DAC (nominal 16 kΩ to AVSS for 2 mA output) when internal QRSET is disabled; serves as auxiliary Q DAC output AUXQ when internal QRSET is enabled.
33 FSADJI/AUXI passive Full-scale current adjust for I DAC (nominal 16 kΩ to AVSS for 2 mA output) when internal IRSET is disabled; serves as auxiliary I DAC output AUXI when internal IRSET is enabled.
34 REFIO bidirectional Reference input when the internal reference is disabled; provides a 1.0 V reference output in internal mode and requires a 0.1 μF capacitor to AVSS.
35 RESET/PINMD input Logic low (pull-down to DVSS) selects SPI mode and a logic high pulse of at least 50 ns followed by logic low resets the SPI registers; logic high (pull-up to DVDDIO) selects pin mode.
36 SCLK/CLKMD input In SPI mode this is the serial clock input with a maximum frequency of 20 MHz; in pin mode it sets the retiming clock phase (tie to 0 when DCLKIO = CLKIN, otherwise pulse 0 to 1).
37 SDIO/FORMAT bidirectional In SPI mode this is the bidirectional serial data line; in pin mode a logic low selects binary input format and a logic high (pull-up to DVDDIO) selects two's complement format.
38 CS/PWRDN input In SPI mode this is the active-low chip select; in pin mode a logic high (pull-up to DVDDIO) powers down the device except the SPI port.
39 DB13 input Digital data input MSB DB13; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
40 DB12 input Digital data input bit DB12; absolute maximum range is −0.3 V to DVDDIO + 0.3 V referenced to DVSS.
41 EPAD power_in Exposed pad connected to AVSS that should be soldered to the ground plane; exposed metal at the package corners is connected to this pad.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-40(6x6)
Category Data Converters
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Offset Error -1 0 1 mV 5
Gain Error -2 2 % of FSR Internal reference 5
Full-Scale Output Current IxOUTFS 1 2 4 mA AVDD = 3.3 V; based on a 10 kΩ external resistor (table footnote 1) 5
Full-Scale Output Current IxOUTFS 1 2 2.5 mA AVDD = 1.8 V; based on a 10 kΩ external resistor (table footnote 1) 5
Output Compliance Range -0.5 0 1.2 V 5
Main DAC Gain Drift -40 40 ppm/°C 5
Main DAC Reference Voltage Drift -25 25 ppm/°C 5
Internal Reference Voltage 0.98 1.025 1.08 V 6
Reference Input Voltage Compliance 0.1 1.25 V AVDD = 3.3 V 6
Reference Input Voltage Compliance 0.1 1 V AVDD = 1.8 V 6
Gain Matching -1 1 % FSR 6
AVDD Analog Supply Voltage AVDD 1.7 3.5 V 6
CVDD Sampling Clock Supply Voltage CVDD 1.7 3.5 V 6
DVDD Digital Core Supply Voltage DVDD 1.7 1.9 V 6
DVDDIO Digital I/O Supply Voltage DVDDIO 1.7 3.5 V 6
Operating Range -40 25 85 °C TMIN to TMAX 6
DAC Clock Input VIH VIH 2.1 3 V DAC clock input (CLKIN) 7
DAC Clock Input VIL VIL 0 0.9 V DAC clock input (CLKIN) 7
Maximum Clock Rate 125 MSPS DAC clock input (CLKIN) 7
Maximum Clock Rate (SCLK) 25 MHz Serial peripheral interface 7
Minimum Pulse Width High 20 ns Serial peripheral interface 7
Minimum Pulse Width Low 20 ns Serial peripheral interface 7
AVDD, DVDDIO, CVDD to AVSS, DVSS, CVSS -0.3 3.9 V 9
DVDD to DVSS -0.3 2.1 V 9
AVSS to DVSS, CVSS -0.3 0.3 V 9
DVSS to AVSS, CVSS -0.3 0.3 V 9
CVSS to AVSS, DVSS -0.3 0.3 V 9
REFIO, FSADJQ, FSADJI, CMLQ, CMLI to AVSS -0.3 V Upper limit printed as AVDD + 0.3 V (not evaluated) 9
QOUTP, QOUTN, IOUTP, IOUTN, RLQP, RLQN, RLIP, RLIN to AVSS -1 V Upper limit printed as AVDD + 0.3 V (not evaluated) 9
DB13 (MSB) to DB0 (LSB), CS, SCLK, SDIO, RESET to DVSS -0.3 V Upper limit printed as DVDDIO + 0.3 V (not evaluated); DB13 per footnote n = 13 for AD9717 9
CLKIN to CVSS -0.3 V Upper limit printed as CVDD + 0.3 V (not evaluated) 9
Junction Temperature 125 °C 9
Storage Temperature Range -65 150 °C 9
Junction-to-Ambient Thermal Resistance θJA 29.8 °C/W 40-lead LFCSP, no airflow movement 9
Junction-to-Board Thermal Resistance θJB 19 °C/W 40-lead LFCSP, JEDEC multilayer test board 9
Junction-to-Case Thermal Resistance θJC 3.4 °C/W 40-lead LFCSP, JEDEC multilayer test board 9

CAD (KiCad official)

  • Symbol: AD9717BCPZ
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: LFCSP-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: ad9717bcpz-etched.step / ad9717bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9717bcpz.step / ad9717bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (54 pp, sha256 5ea573ba516b2167, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF