component
AD9545BCPZ
Public Made by Adomby adom
Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "ad9545bcpz",
"title": "AD9545BCPZ",
"brief": "Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"rtc-clock chip",
"ad9545bcpz",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "AD9545BCPZ",
"manufacturer": "Analog Devices",
"package": "LFCSP-48(7x7)",
"pin_count": 49,
"category": "RTC/Clock Chip",
"subcategory": "Clock Generators / Frequency Synthesizers / PLL",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9545.pdf",
"parts": {
"symbol": "ad9545bcpz.kicad_sym",
"footprint": "ad9545bcpz.kicad_mod",
"model_3d": "ad9545bcpz-hero.glb",
"model_3d_plain": "ad9545bcpz-etched.glb",
"model_3d_step": "ad9545bcpz-etched.step",
"model_3d_step_plain": "ad9545bcpz.step",
"lbr": "ad9545bcpz.lbr"
},
"distributor_links": {
"lcsc": "C653562",
"digikey": "505-AD9545BCPZ-ND",
"mouser": "584-AD9545BCPZ"
},
"distributor_check": {
"checked_at": "2026-10-30T17:02:01Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "505-AD9545BCPZ-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD9545BCPZ",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "SDO/M5",
"type": "output",
"description": "Serial data output (SDO) for 4-wire SPI reads; when not in 4-wire SPI mode it is configurable status/control pin M5, and VDDIOA sets its VIH and VOH levels."
},
{
"number": "2",
"name": "SCLK/SCL",
"type": "input",
"description": "Serial clock input in SPI mode (maximum 50 MHz) or serial clock (SCL) in I²C mode; VDDIOA sets its VIH and VOH levels."
},
{
"number": "3",
"name": "VDDIOA",
"type": "power_in",
"description": "Serial port power supply; valid supply is 1.8 V, 2.5 V, or 3.3 V, and it may be tied to VDD for 1.8 V operation."
},
{
"number": "4",
"name": "SDIO/SDA",
"type": "bidirectional",
"description": "Serial data input/output in SPI mode (SDIO) or serial data line in I²C mode (SDA); no internal pull-up or pull-down, and VDDIOA sets its VIH and VOH levels."
},
{
"number": "5",
"name": "CSB/M6",
"type": "bidirectional",
"description": "Active-low chip select in SPI mode (internal 10 kΩ pull-up, hold low during SPI programming); when not in SPI mode it is configurable status/control pin M6."
},
{
"number": "6",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "7",
"name": "LDO0",
"type": "input",
"description": "LDO bypass for the APLL0 loop filter voltage regulator; connect a 0.22 µF capacitor from this pin to ground, which is the AC ground reference for the APLL0 loop filter."
},
{
"number": "8",
"name": "LF0",
"type": "passive",
"description": "Loop filter node for APLL0; connect a 3.9 nF capacitor from this pin to pin 7 (LDO0)."
},
{
"number": "9",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "10",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "11",
"name": "OUT0AP",
"type": "output",
"description": "PLL0 output 0A, configurable as HCSL, LVDS, or CML."
},
{
"number": "12",
"name": "OUT0AN",
"type": "output",
"description": "PLL0 complementary output 0A, configurable as HCSL, LVDS, or CML."
},
{
"number": "13",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "14",
"name": "OUT0BP",
"type": "output",
"description": "PLL0 output 0B, configurable as HCSL, LVDS, or CML."
},
{
"number": "15",
"name": "OUT0BN",
"type": "output",
"description": "PLL0 complementary output 0B, configurable as HCSL, LVDS, or CML."
},
{
"number": "16",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; leave floating."
},
{
"number": "17",
"name": "OUT0CP",
"type": "output",
"description": "PLL0 output 0C, configurable as HCSL, LVDS, or CML."
},
{
"number": "18",
"name": "OUT0CN",
"type": "output",
"description": "PLL0 complementary output 0C, configurable as HCSL, LVDS, or CML."
},
{
"number": "19",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "20",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "21",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; leave floating."
},
{
"number": "22",
"name": "OUT1BP",
"type": "output",
"description": "PLL1 output 1B, configurable as HCSL, LVDS, or CML."
},
{
"number": "23",
"name": "OUT1BN",
"type": "output",
"description": "PLL1 complementary output 1B, configurable as HCSL, LVDS, or CML."
},
{
"number": "24",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "25",
"name": "OUT1AP",
"type": "output",
"description": "PLL1 output 1A, configurable as HCSL, LVDS, or CML."
},
{
"number": "26",
"name": "OUT1AN",
"type": "output",
"description": "PLL1 complementary output 1A, configurable as HCSL, LVDS, or CML (datasheet lists the type as Input/Output)."
},
{
"number": "27",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "28",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "29",
"name": "LF1",
"type": "passive",
"description": "Loop filter node for APLL1; connect a 3.9 nF capacitor from this pin to pin 30 (LDO1)."
},
{
"number": "30",
"name": "LDO1",
"type": "input",
"description": "LDO bypass for the APLL1 loop filter voltage regulator; connect a 0.22 µF capacitor from this pin to ground, which is the AC ground reference for the APLL1 loop filter."
},
{
"number": "31",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "32",
"name": "M0",
"type": "bidirectional",
"description": "Configurable status/control pin M0 with no internal resistor; VDDIOB sets its VIH and VOH levels."
},
{
"number": "33",
"name": "M1",
"type": "bidirectional",
"description": "Configurable status/control pin M1 with no internal resistor; VDDIOB sets its VIH and VOH levels."
},
{
"number": "34",
"name": "VDDIOB",
"type": "power_in",
"description": "Mx pin power supply for M0 to M4; valid supply is 1.8 V, 2.5 V, or 3.3 V, and it may be tied to VDD for 1.8 V operation."
},
{
"number": "35",
"name": "M2",
"type": "bidirectional",
"description": "Configurable status/control pin M2 with no internal resistor; VDDIOB sets its VIH and VOH levels."
},
{
"number": "36",
"name": "M3",
"type": "bidirectional",
"description": "Configurable status/control pin M3 with internal 100 kΩ pull-down; at startup it selects EEPROM load (logic 1 loads from EEPROM)."
},
{
"number": "37",
"name": "M4",
"type": "bidirectional",
"description": "Configurable status/control pin M4 with internal 100 kΩ pull-down; at startup it selects the serial port (logic 1 = I²C, logic 0 = SPI)."
},
{
"number": "38",
"name": "REFB",
"type": "input",
"description": "Reference B input, internally biased and typically ac-coupled; accepts 1.8 V single-ended or differential signals with swing up to VDD, or LVDS/1.8 V CMOS when dc-coupled."
},
{
"number": "39",
"name": "REFBB",
"type": "input",
"description": "Complementary reference B input when REFB is differential; leave unconnected if REFB is single-ended and REFBB is not used."
},
{
"number": "40",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "41",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "42",
"name": "XOA",
"type": "input",
"description": "System clock input, internally biased and ac-coupled with 0.1 µF except when a crystal is used (crystal connects across XOA and XOB); a single-ended CMOS input can produce spurs when duty cycle is not 50%."
},
{
"number": "43",
"name": "XOB",
"type": "input",
"description": "Complementary system clock input to XOA, internally biased and ac-coupled with 0.1 µF except with a crystal; for single-ended use connect a 0.1 µF capacitor from XOB to ground."
},
{
"number": "44",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; leave floating."
},
{
"number": "45",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "46",
"name": "REFAA",
"type": "input",
"description": "Complementary reference A input when REFA is differential; if dc-coupled the input is single-ended 1.8 V CMOS, and it need not be connected when REFA is single-ended."
},
{
"number": "47",
"name": "REFA",
"type": "input",
"description": "Reference A input, internally biased and typically ac-coupled; accepts 1.8 V single-ended or differential signals with swing up to VDD, or LVDS/1.8 V CMOS when dc-coupled."
},
{
"number": "48",
"name": "RESETB",
"type": "input",
"description": "Active-low chip reset with internal 100 kΩ pull-up; asserting it puts the chip into reset, and VDDIOA sets its VIH level."
},
{
"number": "49",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The exposed pad is not numbered in the datasheet; it is listed as 'EPAD' in the pin table and is the; Datasheet Table 34 lists OUT1AN type as 'Input/Output' while its description is a PLL1 complementary; SDO/M5 and CSB/M6 are multifunction pins; the table lists SDO/M5 as Output and CSB/M6 as Input/outpu",
"exposed pad 49 added from the footprint",
"dropped thermal pad ['EP'] absent from footprint"
],
"pages_sent": 42,
"cost_usd": 0.2987,
"at": "2026-10-30T17:01:45"
},
"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9545.pdf",
"pages": 173,
"sha256": "7a0d5c1554346eee",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 49,
"described": 49,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad9545bcpz.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
7,
7,
0.77
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad9545bcpz-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
7,
7,
0.77
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "c16ed87ec598424ae27ecf5b18ace9c632c0d16728a569cb56dd32c79fb90ddb",
"checked": "2026-10-30",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "CP-48-13",
"source_page": 173,
"D": {
"nom_mm": 7,
"range_mm": [
6.9,
7.1
]
},
"E1": {
"nom_mm": 7,
"range_mm": [
6.9,
7.1
]
},
"e": {
"nom_mm": 0.5,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 0.75,
"range_mm": [
0.7,
0.8
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "ad9545bcpz.step",
"verdict": "PASS",
"reasons": [
"height within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
},
"metadata": {
"specs": {
"Manufacturer": "Analog Devices",
"Package": "LFCSP-48(7x7)",
"Category": "RTC/Clock Chip",
"Pins": "49"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "7a0d5c1554346eee60714715e6775a6b8953aa14268ce15855c183ea26dc8578",
"rows": [
{
"name": "Operating temperature range",
"symbol": "",
"kind": "recommended_operating",
"unit": "°C",
"min": -40,
"typ": null,
"max": 85,
"conditions": "Device operating temperature range (General Description)",
"source_page": 1,
"source": "datasheet"
},
{
"name": "System clock input frequency (XOA/XOB)",
"symbol": "",
"kind": "recommended_operating",
"unit": "MHz",
"min": 20,
"typ": null,
"max": 300,
"conditions": "External clock source on XOA/XOB",
"source_page": 45,
"source": "datasheet"
},
{
"name": "Crystal resonator frequency (across XOA and XOB)",
"symbol": "",
"kind": "recommended_operating",
"unit": "MHz",
"min": 25,
"typ": null,
"max": 80,
"conditions": "Crystal connected directly across XOA and XOB",
"source_page": 45,
"source": "datasheet"
},
{
"name": "Distribution output driver maximum frequency",
"symbol": "",
"kind": "recommended_operating",
"unit": "MHz",
"min": null,
"typ": null,
"max": 500,
"conditions": "Clock output drivers operate up to 500 MHz",
"source_page": 45,
"source": "datasheet"
},
{
"name": "Digital Phase Detector (DPD) input frequency range",
"symbol": "",
"kind": "electrical",
"unit": "Hz",
"min": 1,
"typ": null,
"max": null,
"conditions": "Upper limit printed as 2 × 10^5 Hz (not representable as number)",
"source_page": 23,
"source": "datasheet"
},
{
"name": "Loop filter bandwidth, Profile 0",
"symbol": "",
"kind": "electrical",
"unit": "Hz",
"min": 0.0001,
"typ": null,
"max": 1850,
"conditions": "Programmable design parameter; (fPFD/bandwidth) ≥ 20",
"source_page": 23,
"source": "datasheet"
},
{
"name": "Loop filter bandwidth, Profile 1",
"symbol": "",
"kind": "electrical",
"unit": "Hz",
"min": 0.0001,
"typ": null,
"max": 305,
"conditions": "Programmable design parameter; (fPFD/bandwidth) ≥ 20",
"source_page": 23,
"source": "datasheet"
},
{
"name": "DPLL NCO division integer portion",
"symbol": "",
"kind": "electrical",
"unit": "",
"min": 7,
"typ": null,
"max": 13,
"conditions": "NCO division = 248/FTW0 (as printed); integer portion",
"source_page": 23,
"source": "datasheet"
},
{
"name": "DPLL NCO division fractional portion",
"symbol": "",
"kind": "electrical",
"unit": "",
"min": 0.05,
"typ": null,
"max": 0.95,
"conditions": "NCO division = 248/FTW0 (as printed); fractional portion",
"source_page": 23,
"source": "datasheet"
},
{
"name": "Phase lock detector threshold programming range",
"symbol": "",
"kind": "electrical",
"unit": "ps",
"min": 10,
"typ": null,
"max": null,
"conditions": "Upper limit printed as 2^24 − 1 (not representable as number)",
"source_page": 23,
"source": "datasheet"
},
{
"name": "Frequency lock detector threshold programming range",
"symbol": "",
"kind": "electrical",
"unit": "ps",
"min": 10,
"typ": null,
"max": null,
"conditions": "Upper limit printed as 2^24 − 1 (not representable as number)",
"source_page": 23,
"source": "datasheet"
},
{
"name": "Phase step detector threshold programming range",
"symbol": "",
"kind": "electrical",
"unit": "ps",
"min": 100,
"typ": null,
"max": null,
"conditions": "Upper limit printed as 2^32 − 1; setting too low causes false triggers",
"source_page": 23,
"source": "datasheet"
},
{
"name": "Maximum output phase perturbation, peak (phase refinement disabled)",
"symbol": "",
"kind": "electrical",
"unit": "ps",
"min": -140,
"typ": null,
"max": 140,
"conditions": "Phase refinement disabled; 50 Hz DPLL BW; normal phase margin; reference switch by fault",
"source_page": 24,
"source": "datasheet"
},
{
"name": "Maximum output phase perturbation, steady state, phase buildout (phase refinement disabled)",
"symbol": "",
"kind": "electrical",
"unit": "ps",
"min": -125,
"typ": null,
"max": 125,
"conditions": "Phase refinement disabled; phase buildout operation; 50 Hz DPLL BW",
"source_page": 24,
"source": "datasheet"
},
{
"name": "Maximum output phase perturbation, peak (phase refinement enabled)",
"symbol": "",
"kind": "electrical",
"unit": "ps",
"min": -40,
"typ": null,
"max": 40,
"conditions": "Phase refinement enabled; 50 Hz DPLL BW; high phase margin; 4 refinement iterations",
"source_page": 24,
"source": "datasheet"
},
{
"name": "Maximum output phase perturbation, steady state, phase buildout (phase refinement enabled)",
"symbol": "",
"kind": "electrical",
"unit": "ps",
"min": -35,
"typ": null,
"max": 35,
"conditions": "Phase refinement enabled; phase buildout operation; 50 Hz DPLL BW",
"source_page": 24,
"source": "datasheet"
},
{
"name": "Phase slew limiter",
"symbol": "",
"kind": "electrical",
"unit": "µs/sec",
"min": 0.001,
"typ": null,
"max": 250,
"conditions": "See AN-1420 Application Note",
"source_page": 24,
"source": "datasheet"
},
{
"name": "DPLL propagation delay, LVDS ref, Differential HCSL out",
"symbol": "",
"kind": "timing",
"unit": "ps",
"min": 430,
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