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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9545BCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-48(7x7)

AD9545BCPZ from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	SDO/M5	output	Serial data output (SDO) for 4-wire SPI reads; when not in 4-wire SPI mode it is configurable status/control pin M5, and VDDIOA sets its VIH and VOH levels.
2	SCLK/SCL	input	Serial clock input in SPI mode (maximum 50 MHz) or serial clock (SCL) in I²C mode; VDDIOA sets its VIH and VOH levels.
3	VDDIOA	power_in	Serial port power supply; valid supply is 1.8 V, 2.5 V, or 3.3 V, and it may be tied to VDD for 1.8 V operation.
4	SDIO/SDA	bidirectional	Serial data input/output in SPI mode (SDIO) or serial data line in I²C mode (SDA); no internal pull-up or pull-down, and VDDIOA sets its VIH and VOH levels.
5	CSB/M6	bidirectional	Active-low chip select in SPI mode (internal 10 kΩ pull-up, hold low during SPI programming); when not in SPI mode it is configurable status/control pin M6.
6	VDD	power_in	1.8 V power supply.
7	LDO0	input	LDO bypass for the APLL0 loop filter voltage regulator; connect a 0.22 µF capacitor from this pin to ground, which is the AC ground reference for the APLL0 loop filter.
8	LF0	passive	Loop filter node for APLL0; connect a 3.9 nF capacitor from this pin to pin 7 (LDO0).
9	VDD	power_in	1.8 V power supply.
10	VDD	power_in	1.8 V power supply.
11	OUT0AP	output	PLL0 output 0A, configurable as HCSL, LVDS, or CML.
12	OUT0AN	output	PLL0 complementary output 0A, configurable as HCSL, LVDS, or CML.
13	VDD	power_in	1.8 V power supply.
14	OUT0BP	output	PLL0 output 0B, configurable as HCSL, LVDS, or CML.
15	OUT0BN	output	PLL0 complementary output 0B, configurable as HCSL, LVDS, or CML.
16	DNC	unconnected	Do not connect; leave floating.
17	OUT0CP	output	PLL0 output 0C, configurable as HCSL, LVDS, or CML.
18	OUT0CN	output	PLL0 complementary output 0C, configurable as HCSL, LVDS, or CML.
19	VDD	power_in	1.8 V power supply.
20	VDD	power_in	1.8 V power supply.
21	DNC	unconnected	Do not connect; leave floating.
22	OUT1BP	output	PLL1 output 1B, configurable as HCSL, LVDS, or CML.
23	OUT1BN	output	PLL1 complementary output 1B, configurable as HCSL, LVDS, or CML.
24	VDD	power_in	1.8 V power supply.
25	OUT1AP	output	PLL1 output 1A, configurable as HCSL, LVDS, or CML.
26	OUT1AN	output	PLL1 complementary output 1A, configurable as HCSL, LVDS, or CML (datasheet lists the type as Input/Output).
27	VDD	power_in	1.8 V power supply.
28	VDD	power_in	1.8 V power supply.
29	LF1	passive	Loop filter node for APLL1; connect a 3.9 nF capacitor from this pin to pin 30 (LDO1).
30	LDO1	input	LDO bypass for the APLL1 loop filter voltage regulator; connect a 0.22 µF capacitor from this pin to ground, which is the AC ground reference for the APLL1 loop filter.
31	VDD	power_in	1.8 V power supply.
32	M0	bidirectional	Configurable status/control pin M0 with no internal resistor; VDDIOB sets its VIH and VOH levels.
33	M1	bidirectional	Configurable status/control pin M1 with no internal resistor; VDDIOB sets its VIH and VOH levels.
34	VDDIOB	power_in	Mx pin power supply for M0 to M4; valid supply is 1.8 V, 2.5 V, or 3.3 V, and it may be tied to VDD for 1.8 V operation.
35	M2	bidirectional	Configurable status/control pin M2 with no internal resistor; VDDIOB sets its VIH and VOH levels.
36	M3	bidirectional	Configurable status/control pin M3 with internal 100 kΩ pull-down; at startup it selects EEPROM load (logic 1 loads from EEPROM).
37	M4	bidirectional	Configurable status/control pin M4 with internal 100 kΩ pull-down; at startup it selects the serial port (logic 1 = I²C, logic 0 = SPI).
38	REFB	input	Reference B input, internally biased and typically ac-coupled; accepts 1.8 V single-ended or differential signals with swing up to VDD, or LVDS/1.8 V CMOS when dc-coupled.
39	REFBB	input	Complementary reference B input when REFB is differential; leave unconnected if REFB is single-ended and REFBB is not used.
40	VDD	power_in	1.8 V power supply.
41	VDD	power_in	1.8 V power supply.
42	XOA	input	System clock input, internally biased and ac-coupled with 0.1 µF except when a crystal is used (crystal connects across XOA and XOB); a single-ended CMOS input can produce spurs when duty cycle is not 50%.
43	XOB	input	Complementary system clock input to XOA, internally biased and ac-coupled with 0.1 µF except with a crystal; for single-ended use connect a 0.1 µF capacitor from XOB to ground.
44	DNC	unconnected	Do not connect; leave floating.
45	VDD	power_in	1.8 V power supply.
46	REFAA	input	Complementary reference A input when REFA is differential; if dc-coupled the input is single-ended 1.8 V CMOS, and it need not be connected when REFA is single-ended.
47	REFA	input	Reference A input, internally biased and typically ac-coupled; accepts 1.8 V single-ended or differential signals with swing up to VDD, or LVDS/1.8 V CMOS when dc-coupled.
48	RESETB	input	Active-low chip reset with internal 100 kΩ pull-up; asserting it puts the chip into reset, and VDDIOA sets its VIH level.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Analog Devices
Package	LFCSP-48(7x7)
Category	RTC/Clock Chip
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating temperature range		-40		85	°C	Device operating temperature range (General Description)	1
System clock input frequency (XOA/XOB)		20		300	MHz	External clock source on XOA/XOB	45
Crystal resonator frequency (across XOA and XOB)		25		80	MHz	Crystal connected directly across XOA and XOB	45
Distribution output driver maximum frequency				500	MHz	Clock output drivers operate up to 500 MHz	45
Digital Phase Detector (DPD) input frequency range		1			Hz	Upper limit printed as 2 × 10^5 Hz (not representable as number)	23
Loop filter bandwidth, Profile 0		0.0001		1850	Hz	Programmable design parameter; (fPFD/bandwidth) ≥ 20	23
Loop filter bandwidth, Profile 1		0.0001		305	Hz	Programmable design parameter; (fPFD/bandwidth) ≥ 20	23
DPLL NCO division integer portion		7		13		NCO division = 248/FTW0 (as printed); integer portion	23
DPLL NCO division fractional portion		0.05		0.95		NCO division = 248/FTW0 (as printed); fractional portion	23
Phase lock detector threshold programming range		10			ps	Upper limit printed as 2^24 − 1 (not representable as number)	23
Frequency lock detector threshold programming range		10			ps	Upper limit printed as 2^24 − 1 (not representable as number)	23
Phase step detector threshold programming range		100			ps	Upper limit printed as 2^32 − 1; setting too low causes false triggers	23
Maximum output phase perturbation, peak (phase refinement disabled)		-140		140	ps	Phase refinement disabled; 50 Hz DPLL BW; normal phase margin; reference switch by fault	24
Maximum output phase perturbation, steady state, phase buildout (phase refinement disabled)		-125		125	ps	Phase refinement disabled; phase buildout operation; 50 Hz DPLL BW	24
Maximum output phase perturbation, peak (phase refinement enabled)		-40		40	ps	Phase refinement enabled; 50 Hz DPLL BW; high phase margin; 4 refinement iterations	24
Maximum output phase perturbation, steady state, phase buildout (phase refinement enabled)		-35		35	ps	Phase refinement enabled; phase buildout operation; 50 Hz DPLL BW	24
Phase slew limiter		0.001		250	µs/sec	See AN-1420 Application Note	24
DPLL propagation delay, LVDS ref, Differential HCSL out		430	810	1120	ps	Ref LVDS ac-coupled; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, LVDS ref, Differential CML out		390	780	1090	ps	Ref LVDS ac-coupled; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, LVDS ref, Single-Ended HCSL out		330	890	1360	ps	Ref LVDS ac-coupled; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, LVDS ref, Single-Ended CML out		295	760	1155	ps	Ref LVDS ac-coupled; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, 1.2 V CMOS ref, Differential HCSL out		-390	-100	195	ps	Single-ended 1.2 V CMOS ref; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, 1.2 V CMOS ref, Differential CML out		-415	-130	150	ps	Single-ended 1.2 V CMOS ref; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, 1.2 V CMOS ref, Single-Ended HCSL out		-450	-150	160	ps	Single-ended 1.2 V CMOS ref; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, 1.2 V CMOS ref, Single-Ended CML out		-440	-105	235	ps	Single-ended 1.2 V CMOS ref; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, 1.8 V CMOS ref, Differential HCSL out		-270	100	420	ps	Single-ended 1.8 V CMOS ref; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, 1.8 V CMOS ref, Differential CML out		-285	70	380	ps	Single-ended 1.8 V CMOS ref; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, 1.8 V CMOS ref, Single-Ended HCSL out		-360	30	335	ps	Single-ended 1.8 V CMOS ref; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
DPLL propagation delay, 1.8 V CMOS ref, Single-Ended CML out		-315	105	460	ps	Single-ended 1.8 V CMOS ref; internal zero delay, 1:1, fREF = fOUT = 50 MHz; delay compensation inactive	25
1.8 V supply voltage (VDD) absolute maximum	VDD			2	V		36
Output driver pins voltage absolute maximum (OUTxyP/OUTxyN)				2	V	OUTA0P/N, OUTB0P/N, OUTC0P/N, OUTA1P/N, OUTB1P/N pins	36
Input/output supply voltage absolute maximum (VDDIOA, VDDIOB)	VDDIOA, VDDIOB			3.6	V		36
Input voltage range (XOA, XOB, REFA, REFAA, REFB, REFBB)		-0.5			V	Maximum printed as VDD + 0.5 V	36
Digital input voltage range (SDO/M5, SCLK/SCL, SDIO/SDA, CSB/M6)		-0.5			V	Maximum printed as VDDIOA + 0.5 V	36
Digital input voltage range (M0 to M4)		-0.5			V	Maximum printed as VDDIOB + 0.5 V	36
Storage temperature range		-65		150	°C		36
Lead temperature (soldering)				300	°C	Soldering, 10 sec	36
Thermal resistance, junction to ambient (θJA)	θJA		23.9		°C/W	0.0 m/sec airflow, JEDEC JESD51-2 (still air); package CP-48-132	36
Thermal resistance, junction to ambient, moving air (θJMA)	θJMA		19.4		°C/W	1.0 m/sec airflow, JEDEC JESD51-6	36
Thermal resistance, junction to ambient, moving air (θJMA)	θJMA		18.2		°C/W	2.5 m/sec airflow, JEDEC JESD51-6	36
Thermal resistance, junction to case (θJC)	θJC		1.5		°C/W	Die to heat sink, MIL-STD 883 Method 1012.1; package CP-48-132	36

CAD (KiCad official)

Symbol: AD9545BCPZ
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
3D model files: ad9545bcpz-etched.step / ad9545bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9545bcpz.step / ad9545bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Analog Devices datasheet (173 pp, sha256 7a0d5c1554346eee, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

AD9545BCPZ

Verified AD9545BCPZ

Verification log 1 record

AD9545BCPZ

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance