component
AD9543BCPZ
Public Made by Adomby adom
Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"schema_version": 1,
"type": "component",
"slug": "ad9543bcpz",
"title": "AD9543BCPZ",
"brief": "Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"version": "0.1.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"rtc-clock chip",
"ad9543bcpz",
"factory-2.0.0",
"extractor-text"
],
"component": {
"mpn": "AD9543BCPZ",
"manufacturer": "Analog Devices",
"package": "LFCSP-48(7x7)",
"pin_count": 49,
"category": "RTC/Clock Chip",
"subcategory": "Clock Generators / Frequency Synthesizers / PLL",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9543.pdf",
"parts": {
"symbol": "ad9543bcpz.kicad_sym",
"footprint": "ad9543bcpz.kicad_mod",
"model_3d": "ad9543bcpz-hero.glb",
"model_3d_plain": "ad9543bcpz-etched.glb",
"model_3d_step": "ad9543bcpz-etched.step",
"model_3d_step_plain": "ad9543bcpz.step",
"lbr": "ad9543bcpz.lbr"
},
"distributor_links": {
"lcsc": "C653558",
"digikey": "AD9543BCPZ-ND",
"mouser": "584-AD9543BCPZ"
},
"distributor_check": {
"checked_at": "2026-10-28T15:59:39Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "AD9543BCPZ-ND",
"status": "found"
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"mouser": {
"pn": "584-AD9543BCPZ",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "SDO/M5",
"type": "output",
"description": "Serial data output (SDO) for reading data in 4-wire SPI mode; M5 is a configurable status/control pin when the device is not in 4-wire SPI mode, and its VOH follows VDDIOA."
},
{
"number": "2",
"name": "SCLK/SCL",
"type": "input",
"description": "Serial programming clock (SCLK) in SPI mode or serial clock (SCL) in I2C mode; VIH and VOH follow the VDDIOA supply."
},
{
"number": "3",
"name": "VDDIOA",
"type": "power_in",
"description": "Serial port power supply, valid at 1.8 V, 2.5 V or 3.3 V; may be connected to VDD for 1.8 V operation."
},
{
"number": "4",
"name": "SDIO/SDA",
"type": "bidirectional",
"description": "Serial data input/output (SDIO) in SPI mode with no internal pull-up or pull-down; serial data (SDA) in I2C mode."
},
{
"number": "5",
"name": "CSB/M6",
"type": "bidirectional",
"description": "Active-low chip select (CSB) in SPI mode with an internal 10 kΩ pull-up; M6 is a configurable status/control pin when not in SPI mode."
},
{
"number": "6",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "7",
"name": "LDO0",
"type": "input",
"description": "LDO bypass for the APLL0 loop filter voltage regulator; connect a 0.22 µF capacitor from this pin to ground."
},
{
"number": "8",
"name": "LF0",
"type": "passive",
"description": "APLL0 loop filter node; connect a 3.9 nF capacitor from this pin to pin 7 (LDO0)."
},
{
"number": "9",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "10",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "11",
"name": "OUT0AP",
"type": "output",
"description": "PLL0 output 0A, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "12",
"name": "OUT0AN",
"type": "output",
"description": "PLL0 complementary output 0A, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "13",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "14",
"name": "OUT0BP",
"type": "output",
"description": "PLL0 output 0B, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "15",
"name": "OUT0BN",
"type": "output",
"description": "PLL0 complementary output 0B, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "16",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; leave floating."
},
{
"number": "17",
"name": "OUT0CP",
"type": "output",
"description": "PLL0 output 0C, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "18",
"name": "OUT0CN",
"type": "output",
"description": "PLL0 complementary output 0C, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "19",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "20",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "21",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; leave floating."
},
{
"number": "22",
"name": "OUT1BP",
"type": "output",
"description": "PLL1 output 1B, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "23",
"name": "OUT1BN",
"type": "output",
"description": "PLL1 complementary output 1B, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "24",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "25",
"name": "OUT1AP",
"type": "output",
"description": "PLL1 output 1A, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "26",
"name": "OUT1AN",
"type": "output",
"description": "PLL1 complementary output 1A, configurable as HCSL, LVDS, CML or CMOS."
},
{
"number": "27",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "28",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "29",
"name": "LF1",
"type": "passive",
"description": "APLL1 loop filter node; connect a 3.9 nF capacitor from this pin to pin 30 (LDO1)."
},
{
"number": "30",
"name": "LDO1",
"type": "input",
"description": "LDO bypass for the APLL1 loop filter voltage regulator; connect a 0.1 µF capacitor from this pin to ground."
},
{
"number": "31",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "32",
"name": "M0",
"type": "bidirectional",
"description": "Configurable status/control pin with no internal resistors; logic levels follow VDDIOB."
},
{
"number": "33",
"name": "M1",
"type": "bidirectional",
"description": "Configurable status/control pin with no internal resistors; logic levels follow VDDIOB."
},
{
"number": "34",
"name": "VDDIOB",
"type": "power_in",
"description": "Mx pin power supply, valid at 1.8 V, 2.5 V or 3.3 V; may be connected to VDD for 1.8 V operation."
},
{
"number": "35",
"name": "M2",
"type": "bidirectional",
"description": "Configurable status/control pin with no internal resistors; logic levels follow VDDIOB."
},
{
"number": "36",
"name": "M3",
"type": "bidirectional",
"description": "Configurable status/control pin with an internal 100 kΩ pull-down resistor; logic levels follow VDDIOB."
},
{
"number": "37",
"name": "M4",
"type": "bidirectional",
"description": "Configurable status/control pin with an internal 100 kΩ pull-down resistor; logic levels follow VDDIOB."
},
{
"number": "38",
"name": "REFB",
"type": "input",
"description": "Reference B input, 1.8 V single-ended or differential; when AC-coupled it accepts a single-ended swing up to VDD, and when DC-coupled it accepts LVDS or 1.8 V CMOS."
},
{
"number": "39",
"name": "REFBB",
"type": "input",
"description": "Complementary reference B input used when REFB is differential; no connection is needed if REFB is single-ended and REFBB is unused."
},
{
"number": "40",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "41",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "42",
"name": "XOA",
"type": "input",
"description": "System clock input, AC-coupled with a 0.01 µF capacitor unless a crystal is used across XOA and XOB; a single-ended CMOS input can produce spurs when the duty cycle is not 50%."
},
{
"number": "43",
"name": "XOB",
"type": "input",
"description": "Complementary system clock input, AC-coupled with a 0.1 µF capacitor unless a crystal is used across XOA and XOB."
},
{
"number": "44",
"name": "DNC",
"type": "unconnected",
"description": "Do not connect; leave floating."
},
{
"number": "45",
"name": "VDD",
"type": "power_in",
"description": "1.8 V power supply."
},
{
"number": "46",
"name": "REFAA",
"type": "input",
"description": "Complementary REFA input when REFA is differential; if DC-coupled the input is single-ended 1.8 V CMOS."
},
{
"number": "47",
"name": "REFA",
"type": "input",
"description": "Reference A input, 1.8 V single-ended or differential; when AC-coupled it accepts a single-ended swing up to VDD, and when DC-coupled it accepts LVDS or 1.8 V CMOS."
},
{
"number": "48",
"name": "RESETB",
"type": "input",
"description": "Active-low chip reset with an internal 100 kΩ pull-up; asserting it puts the chip into reset."
},
{
"number": "49",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Pin assignments are taken from Table 26 (Pin Function Descriptions) because the Figure 2 pin-configu; Table 26 lists OUT1AN with Input/Output in the input/output column, but its function is a PLL1 compl; The exposed pad (EP) is the chip ground. It is recorded as power_in per the ground convention, and t"
],
"pages_sent": 24,
"cost_usd": 0.0554,
"at": "2026-10-28T15:59:23"
},
"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9543.pdf",
"pages": 66,
"sha256": "630ff5aef4e608d1",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 49,
"described": 49,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
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"footprint": "viewers/footprint.html"
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"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "f2b38b0b4bf967c77e683e8d4599608b9f0503055ec535b93c4ebb5d0163e916",
"checked": "2026-10-28",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad9543bcpz-etched.step",
"role": "eda",
"up": "Z",
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"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
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7,
7,
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"zmin_mm": 0,
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"footprint_binding": "identity",
"sha256": "9ecadcba59ad8fa185b6b4a7b77a15b38a3a4199ddbb62ae960923f5cea4bb38",
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},
"metadata": {
"specs": {
"Manufacturer": "Analog Devices",
"Package": "LFCSP-48(7x7)",
"Category": "RTC/Clock Chip",
"Pins": "49"
},
"characteristics": {
"version": 1,
"source": "datasheet",
"datasheet_sha256": "630ff5aef4e608d17784559167100b5b292a6d405838dcc06a60b62e7476ff79",
"rows": [
{
"name": "Validation Timer",
"symbol": "",
"kind": "electrical",
"unit": "sec",
"min": 0.001,
"typ": null,
"max": 1048,
"conditions": "Programmable in 1 ms increments",
"source_page": 8,
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{
"name": "Excess Jitter Alarm Threshold",
"symbol": "",
"kind": "electrical",
"unit": "ns",
"min": 1,
"typ": null,
"max": 65535,
"conditions": "Programmable in 1 ns increments",
"source_page": 8,
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{
"name": "Carrier Frequency Band 0 DC Balanced Modulation",
"symbol": "",
"kind": "electrical",
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"max": 30,
"conditions": "Sync Edge = 1, 2, 3",
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"name": "Carrier Frequency Band 0 Unbalanced Modulation",
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{
"name": "Carrier Frequency Band 1 DC Balanced Modulation",
"symbol": "",
"kind": "electrical",
"unit": "MHz",
"min": 1,
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"max": 90,
"conditions": "Sync Edge = 1, 2, 3",
"source_page": 8,
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"name": "Carrier Frequency Band 1 Unbalanced Modulation",
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"unit": "MHz",
"min": 1,
"typ": null,
"max": 135,
"conditions": "Sync Edge = 1, 2, 3",
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{
"name": "Embedded Clock Rate",
"symbol": "",
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"min": 1,
"typ": null,
"max": null,
"conditions": "Max is fOUT/6 Hz; fOUT is the nominal output frequency of the output with the embedded clock",
"source_page": 8,
"source": "datasheet"
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{
"name": "Maximum Output Phase Perturbation Peak Steady State (Phase Refinement Disabled)",
"symbol": "",
"kind": "timing",
"unit": "ps",
"min": -140,
"typ": null,
"max": 140,
"conditions": "Phase refinement disabled; 50 Hz DPLL loop bandwidth; normal phase margin mode",
"source_page": 9,
"source": "datasheet"
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{
"name": "Maximum Output Phase Perturbation Phase Buildout Operation (Phase Refinement Disabled)",
"symbol": "",
"kind": "timing",
"unit": "ps",
"min": -125,
"typ": null,
"max": 125,
"conditions": "Phase refinement disabled; 50 Hz DPLL loop bandwidth; normal phase margin mode",
"source_page": 9,
"source": "datasheet"
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{
"name": "Maximum Output Phase Perturbation Peak Steady State (Phase Refinement Enabled)",
"symbol": "",
"kind": "timing",
"unit": "ps",
"min": -40,
"typ": null,
"max": 40,
"conditions": "Phase refinement enabled; 50 Hz DPLL loop bandwidth; high phase margin mode; 4 iterations",
"source_page": 9,
"source": "datasheet"
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{
"name": "Maximum Output Phase Perturbation Phase Buildout Operation (Phase Refinement Enabled)",
"symbol": "",
"kind": "timing",
"unit": "ps",
"min": -35,
"typ": null,
"max": 35,
"conditions": "Phase refinement enabled; 50 Hz DPLL loop bandwidth; high phase margin mode; 4 iterations",
"source_page": 9,
"source": "datasheet"
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{
"name": "Phase Slew Limiter",
"symbol": "",
"kind": "timing",
"unit": "µs/sec",
"min": 0.001,
"typ": null,
"max": 250,
"conditions": "See AN-1420",
"source_page": 9,
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{
"name": "HCSL Differential Output Voltage Swing",
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"min": 312,
"typ": 368,
"max": 402,
"conditions": "Output current = 7.5 mA; terminated per Figure 32",
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{
"name": "CML Differential Output Voltage Swing",
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"conditions": "Output current = 7.5 mA; terminated to VDD (nominal 1.8 V) per Figure 33",
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"name": "HCSL Differential Output Voltage Swing",
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"min": 631,
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"name": "CML Differential Output Voltage Swing",
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"min": 578,
"typ": 729,
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"name": "HCSL Common-Mode Output Voltage",
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"conditions": "Output current = 7.5 mA; terminated per Figure 32",
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"name": "HCSL Common-Mode Output Voltage",
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"typ": 372,
"max": 405,
"conditions": "Output current = 15 mA; terminated per Figure 32",
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{
"name": "HCSL Voltage Swing Peak-to-Peak Driver Mode",
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"min": 509,
"typ": 584,
"max": 634,
"conditions": "Single-ended; output current = 12 mA; each output terminated per Figure 37 with RL = 50 Ω",
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"name": "CML Voltage Swing Peak-to-Peak Driver Mode",
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"min": 456,
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"conditions": "Single-ended; output current = 12 mA; each output terminated per Figure 37 with RL = 50 Ω connected to VDD (nominal 1.8 V)",
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{
"name": "HCSL Voltage Swing Midpoint Driver Mode",
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{
"name": "HCSL Voltage Swing Peak-to-Peak Driver Mode",
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"min": 645,
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