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AD9543BCPZ

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD9543BCPZ

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-48(7x7)

AD9543BCPZ from Analog Devices, in a LFCSP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDO/M5 output Serial data output (SDO) for reading data in 4-wire SPI mode; M5 is a configurable status/control pin when the device is not in 4-wire SPI mode, and its VOH follows VDDIOA.
2 SCLK/SCL input Serial programming clock (SCLK) in SPI mode or serial clock (SCL) in I2C mode; VIH and VOH follow the VDDIOA supply.
3 VDDIOA power_in Serial port power supply, valid at 1.8 V, 2.5 V or 3.3 V; may be connected to VDD for 1.8 V operation.
4 SDIO/SDA bidirectional Serial data input/output (SDIO) in SPI mode with no internal pull-up or pull-down; serial data (SDA) in I2C mode.
5 CSB/M6 bidirectional Active-low chip select (CSB) in SPI mode with an internal 10 kΩ pull-up; M6 is a configurable status/control pin when not in SPI mode.
6 VDD power_in 1.8 V power supply.
7 LDO0 input LDO bypass for the APLL0 loop filter voltage regulator; connect a 0.22 µF capacitor from this pin to ground.
8 LF0 passive APLL0 loop filter node; connect a 3.9 nF capacitor from this pin to pin 7 (LDO0).
9 VDD power_in 1.8 V power supply.
10 VDD power_in 1.8 V power supply.
11 OUT0AP output PLL0 output 0A, configurable as HCSL, LVDS, CML or CMOS.
12 OUT0AN output PLL0 complementary output 0A, configurable as HCSL, LVDS, CML or CMOS.
13 VDD power_in 1.8 V power supply.
14 OUT0BP output PLL0 output 0B, configurable as HCSL, LVDS, CML or CMOS.
15 OUT0BN output PLL0 complementary output 0B, configurable as HCSL, LVDS, CML or CMOS.
16 DNC unconnected Do not connect; leave floating.
17 OUT0CP output PLL0 output 0C, configurable as HCSL, LVDS, CML or CMOS.
18 OUT0CN output PLL0 complementary output 0C, configurable as HCSL, LVDS, CML or CMOS.
19 VDD power_in 1.8 V power supply.
20 VDD power_in 1.8 V power supply.
21 DNC unconnected Do not connect; leave floating.
22 OUT1BP output PLL1 output 1B, configurable as HCSL, LVDS, CML or CMOS.
23 OUT1BN output PLL1 complementary output 1B, configurable as HCSL, LVDS, CML or CMOS.
24 VDD power_in 1.8 V power supply.
25 OUT1AP output PLL1 output 1A, configurable as HCSL, LVDS, CML or CMOS.
26 OUT1AN output PLL1 complementary output 1A, configurable as HCSL, LVDS, CML or CMOS.
27 VDD power_in 1.8 V power supply.
28 VDD power_in 1.8 V power supply.
29 LF1 passive APLL1 loop filter node; connect a 3.9 nF capacitor from this pin to pin 30 (LDO1).
30 LDO1 input LDO bypass for the APLL1 loop filter voltage regulator; connect a 0.1 µF capacitor from this pin to ground.
31 VDD power_in 1.8 V power supply.
32 M0 bidirectional Configurable status/control pin with no internal resistors; logic levels follow VDDIOB.
33 M1 bidirectional Configurable status/control pin with no internal resistors; logic levels follow VDDIOB.
34 VDDIOB power_in Mx pin power supply, valid at 1.8 V, 2.5 V or 3.3 V; may be connected to VDD for 1.8 V operation.
35 M2 bidirectional Configurable status/control pin with no internal resistors; logic levels follow VDDIOB.
36 M3 bidirectional Configurable status/control pin with an internal 100 kΩ pull-down resistor; logic levels follow VDDIOB.
37 M4 bidirectional Configurable status/control pin with an internal 100 kΩ pull-down resistor; logic levels follow VDDIOB.
38 REFB input Reference B input, 1.8 V single-ended or differential; when AC-coupled it accepts a single-ended swing up to VDD, and when DC-coupled it accepts LVDS or 1.8 V CMOS.
39 REFBB input Complementary reference B input used when REFB is differential; no connection is needed if REFB is single-ended and REFBB is unused.
40 VDD power_in 1.8 V power supply.
41 VDD power_in 1.8 V power supply.
42 XOA input System clock input, AC-coupled with a 0.01 µF capacitor unless a crystal is used across XOA and XOB; a single-ended CMOS input can produce spurs when the duty cycle is not 50%.
43 XOB input Complementary system clock input, AC-coupled with a 0.1 µF capacitor unless a crystal is used across XOA and XOB.
44 DNC unconnected Do not connect; leave floating.
45 VDD power_in 1.8 V power supply.
46 REFAA input Complementary REFA input when REFA is differential; if DC-coupled the input is single-ended 1.8 V CMOS.
47 REFA input Reference A input, 1.8 V single-ended or differential; when AC-coupled it accepts a single-ended swing up to VDD, and when DC-coupled it accepts LVDS or 1.8 V CMOS.
48 RESETB input Active-low chip reset with an internal 100 kΩ pull-up; asserting it puts the chip into reset.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-48(7x7)
Category RTC/Clock Chip
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Validation Timer 0.001 1048 sec Programmable in 1 ms increments 8
Excess Jitter Alarm Threshold 1 65535 ns Programmable in 1 ns increments 8
Carrier Frequency Band 0 DC Balanced Modulation 0.5 30 MHz Sync Edge = 1, 2, 3 8
Carrier Frequency Band 0 Unbalanced Modulation 0.5 45 MHz Sync Edge = 1, 2, 3 8
Carrier Frequency Band 1 DC Balanced Modulation 1 90 MHz Sync Edge = 1, 2, 3 8
Carrier Frequency Band 1 Unbalanced Modulation 1 135 MHz Sync Edge = 1, 2, 3 8
Embedded Clock Rate 1 Hz Max is fOUT/6 Hz; fOUT is the nominal output frequency of the output with the embedded clock 8
Maximum Output Phase Perturbation Peak Steady State (Phase Refinement Disabled) -140 140 ps Phase refinement disabled; 50 Hz DPLL loop bandwidth; normal phase margin mode 9
Maximum Output Phase Perturbation Phase Buildout Operation (Phase Refinement Disabled) -125 125 ps Phase refinement disabled; 50 Hz DPLL loop bandwidth; normal phase margin mode 9
Maximum Output Phase Perturbation Peak Steady State (Phase Refinement Enabled) -40 40 ps Phase refinement enabled; 50 Hz DPLL loop bandwidth; high phase margin mode; 4 iterations 9
Maximum Output Phase Perturbation Phase Buildout Operation (Phase Refinement Enabled) -35 35 ps Phase refinement enabled; 50 Hz DPLL loop bandwidth; high phase margin mode; 4 iterations 9
Phase Slew Limiter 0.001 250 µs/sec See AN-1420 9
HCSL Differential Output Voltage Swing 312 368 402 mV Output current = 7.5 mA; terminated per Figure 32 9
CML Differential Output Voltage Swing 257 348 408 mV Output current = 7.5 mA; terminated to VDD (nominal 1.8 V) per Figure 33 9
HCSL Differential Output Voltage Swing 631 745 809 mV Output current = 15 mA; terminated per Figure 32 9
CML Differential Output Voltage Swing 578 729 818 mV Output current = 15 mA; terminated to VDD (nominal 1.8 V) per Figure 33 9
HCSL Common-Mode Output Voltage 155 184 201 mV Output current = 7.5 mA; terminated per Figure 32 9
HCSL Common-Mode Output Voltage 316 372 405 mV Output current = 15 mA; terminated per Figure 32 9
HCSL Voltage Swing Peak-to-Peak Driver Mode 509 584 634 mV Single-ended; output current = 12 mA; each output terminated per Figure 37 with RL = 50 Ω 10
CML Voltage Swing Peak-to-Peak Driver Mode 456 565 644 mV Single-ended; output current = 12 mA; each output terminated per Figure 37 with RL = 50 Ω connected to VDD (nominal 1.8 V) 10
HCSL Voltage Swing Midpoint Driver Mode 255 292 317 mV Single-ended; output current = 12 mA; each output terminated per Figure 37 with RL = 50 Ω 10
HCSL Voltage Swing Peak-to-Peak Driver Mode 645 734 796 mV Single-ended; output current = 15 mA; each output terminated per Figure 37 with RL = 50 Ω 10
CML Voltage Swing Peak-to-Peak Driver Mode 589 721 815 mV Single-ended; output current = 15 mA; each output terminated per Figure 37 with RL = 50 Ω connected to VDD (nominal 1.8 V) 10
HCSL Voltage Swing Midpoint Driver Mode 322 367 398 mV Single-ended; output current = 15 mA; each output terminated per Figure 37 with RL = 50 Ω 10
Mx Pin to RESETB Rising Edge Setup Time 1 ns Mx refers to Pin M0 through Pin M6 10
Mx Pin to RESETB Rising Edge Hold Time 2 ns 10
Multiple Mx Pin Timing Skew 39 ns Applies only to multibit Mx pin functions 10
RESETB Falling Edge to Mx Pin High-Z Time 14 ns 10
EEPROM to Register Download Time 10 ms Using the Typical Configuration from Table 3 10
Power-On Reset (POR) 25 ms Time from power supplies > 80% to release of internal reset 10
1.8 V Supply Voltage (VDD) VDD 2 V Absolute maximum rating; 1.8 V supply 21
Input/Output Supply Voltage VDDIOA, VDDIOB 3.6 V Absolute maximum rating 21
Input Voltage Range (XOA, XOB, REFA, REFAA, REFB, REFBB) -0.5 V Upper limit VDD + 0.5 V 21
Digital Input Voltage Range (SDO/M5, SCLK/SCL, SDIO/SDA, CSB/M6) -0.5 V Upper limit VDDIOA + 0.5 V 21
Digital Input Voltage Range (M0, M1, M2, M3, M4) -0.5 V Upper limit VDDIOB + 0.5 V 21
Storage Temperature Range -65 150 °C 21
Operating Temperature Range -40 85 °C See Thermal Resistance section 21
Lead Temperature 300 °C Soldering 10 sec 21
Junction to Ambient Thermal Resistance (still air) θJA 23.9 °C/W Package CP-48-132; 0.0 m/sec airflow per JEDEC JESD51-2 21
Junction to Ambient Thermal Resistance (1.0 m/sec airflow) θJMA 19.4 °C/W Package CP-48-132; 1.0 m/sec airflow per JEDEC JESD51-6 21
Junction to Ambient Thermal Resistance (2.5 m/sec airflow) θJMA 18.2 °C/W Package CP-48-132; 2.5 m/sec airflow per JEDEC JESD51-6 21
Junction to Case Thermal Resistance θJC 1.5 °C/W Package CP-48-132; die to heat sink per MIL-STD 883, Method 1012.1 21

CAD (KiCad official)

  • Symbol: AD9543BCPZ
  • Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
  • 3D model: LFCSP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: ad9543bcpz-etched.step / ad9543bcpz-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9543bcpz.step / ad9543bcpz.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (66 pp, sha256 630ff5aef4e608d1, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF