component
AD9528BCPZ-REEL7
Public Made by Adomby adom
Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584
{
"slug": "ad9528bcpz-reel7",
"version": "0.1.0",
"type": "component",
"description": "Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"clock and timing",
"ad9528bcpz-reel7",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"ad9528bcpz-reel7.kicad_sym",
"ad9528bcpz-reel7.kicad_mod",
"ad9528bcpz-reel7.glb",
"ad9528bcpz-reel7.step",
"ad9528bcpz-reel7.lbr",
"docs/hero.png",
"docs/ad9528bcpz-reel7-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"ad9528bcpz-reel7-hero.glb",
"ad9528bcpz-reel7-hero.overlay.json",
"ad9528bcpz-reel7-etched.glb"
],
"component": {
"mpn": "AD9528BCPZ-REEL7",
"manufacturer": "Analog Devices",
"package": "LFCSP-72(10x10)",
"pin_count": 73,
"category": "Clock and Timing",
"subcategory": "Clock Generators / Frequency Synthesizers / PLL",
"datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9528.pdf",
"parts": {
"symbol": "ad9528bcpz-reel7.kicad_sym",
"footprint": "ad9528bcpz-reel7.kicad_mod",
"model_3d": "ad9528bcpz-reel7-hero.glb",
"model_3d_plain": "ad9528bcpz-reel7-etched.glb",
"model_3d_step": "ad9528bcpz-reel7-etched.step",
"model_3d_step_plain": "ad9528bcpz-reel7.step",
"lbr": "ad9528bcpz-reel7.lbr"
},
"distributor_links": {
"lcsc": "C481893",
"digikey": "505-AD9528BCPZ-REEL7TR-ND",
"mouser": "584-AD9528BCPZ-REEL7"
},
"distributor_check": {
"checked_at": "2026-11-09T06:18:28Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "505-AD9528BCPZ-REEL7TR-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD9528BCPZ-REEL7",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "VDD",
"type": "power_in",
"description": "3.3 V supply for the PLL1 input section."
},
{
"number": "2",
"name": "REFA",
"type": "input",
"description": "Reference clock input A, differential with the complementary pin, or programmable as a single-ended 3.3 V CMOS input."
},
{
"number": "3",
"name": "~{REFA}",
"type": "input",
"description": "Complementary reference clock input A, differential with REFA, or programmable as a single-ended 3.3 V CMOS input."
},
{
"number": "4",
"name": "REF_SEL",
"type": "input",
"description": "Reference input select; defaults to software control via Register 0x010A, Bits[2:0]; when the pin is active, logic low selects REFA and logic high selects REFB."
},
{
"number": "5",
"name": "REFB",
"type": "input",
"description": "Reference clock input B, differential with the complementary pin, or programmable as a single-ended 3.3 V CMOS input."
},
{
"number": "6",
"name": "~{REFB}",
"type": "input",
"description": "Complementary reference clock input B, differential with REFB, or programmable as a single-ended 3.3 V CMOS input."
},
{
"number": "7",
"name": "LF1",
"type": "output",
"description": "PLL1 external loop filter connection."
},
{
"number": "8",
"name": "VCXO_VT",
"type": "output",
"description": "VCXO control voltage; connect to the voltage control pin of the external VCXO."
},
{
"number": "9",
"name": "NIC",
"type": "unconnected",
"description": "Not internally connected; can be left floating."
},
{
"number": "10",
"name": "VDD",
"type": "power_in",
"description": "3.3 V supply for the PLL2 section."
},
{
"number": "11",
"name": "VCXO_IN",
"type": "input",
"description": "PLL1 oscillator input, differential with the complementary pin, or programmable as a single-ended 3.3 V CMOS input."
},
{
"number": "12",
"name": "~{VCXO_IN}",
"type": "input",
"description": "Complementary PLL1 oscillator input, differential with VCXO_IN, or programmable as a single-ended 3.3 V CMOS input."
},
{
"number": "13",
"name": "NIC",
"type": "unconnected",
"description": "Not internally connected; can be left floating."
},
{
"number": "14",
"name": "LF2_CAP",
"type": "output",
"description": "PLL2 external loop filter capacitor connection; connect a capacitor between this pin and the LDO_VCO pin."
},
{
"number": "15",
"name": "LDO_VCO",
"type": "power_out",
"description": "2.5 V LDO internal regulator decoupling for the VCO; connect a 0.47 µF capacitor to ground, placed close to the device."
},
{
"number": "16",
"name": "VDD",
"type": "power_in",
"description": "3.3 V supply for the PLL2 internal regulator."
},
{
"number": "17",
"name": "NIC",
"type": "unconnected",
"description": "Not internally connected; can be left floating."
},
{
"number": "18",
"name": "NIC",
"type": "unconnected",
"description": "Not internally connected; can be left floating."
},
{
"number": "19",
"name": "RESET",
"type": "input",
"description": "Digital input, active low; resets internal logic to default states."
},
{
"number": "20",
"name": "VDD",
"type": "power_in",
"description": "3.3 V supply for the PLL2 internal regulator."
},
{
"number": "21",
"name": "~{CS}",
"type": "input",
"description": "Serial control port chip select, active low, with an internal 35 kΩ pull-up resistor."
},
{
"number": "22",
"name": "SCLK/SCL",
"type": "input",
"description": "Serial control port clock for SPI mode (SCLK) or I2C mode (SCL); data clock for serial programming."
},
{
"number": "23",
"name": "SDIO/SDA",
"type": "bidirectional",
"description": "Serial control port bidirectional data in/out for SPI mode (SDIO) or I2C mode (SDA)."
},
{
"number": "24",
"name": "SDO",
"type": "output",
"description": "Serial data output for reading data in 4-wire mode (high impedance in 3-wire mode); no internal pull-up or pull-down."
},
{
"number": "25",
"name": "OUT13",
"type": "output",
"description": "Square wave clocking output 13."
},
{
"number": "26",
"name": "~{OUT13}",
"type": "output",
"description": "Complementary square wave clocking output 13; high speed output up to 1.25 GHz."
},
{
"number": "27",
"name": "VDD13",
"type": "power_in",
"description": "3.3 V supply for the output 13 clock driver; high speed output up to 1.25 GHz."
},
{
"number": "28",
"name": "OUT12",
"type": "output",
"description": "Square wave clocking output 12; high speed output up to 1.25 GHz."
},
{
"number": "29",
"name": "~{OUT12}",
"type": "output",
"description": "Complementary square wave clocking output 12; high speed output up to 1.25 GHz."
},
{
"number": "30",
"name": "VDD12",
"type": "power_in",
"description": "3.3 V supply for the output 12 clock divider."
},
{
"number": "31",
"name": "OUT11",
"type": "output",
"description": "Square wave clocking output 11."
},
{
"number": "32",
"name": "~{OUT11}",
"type": "output",
"description": "Complementary square wave clocking output 11."
},
{
"number": "33",
"name": "VDD11",
"type": "power_in",
"description": "3.3 V supply for the output 11 clock driver."
},
{
"number": "34",
"name": "OUT10",
"type": "output",
"description": "Square wave clocking output 10."
},
{
"number": "35",
"name": "~{OUT10}",
"type": "output",
"description": "Complementary square wave clocking output 10."
},
{
"number": "36",
"name": "VDD10",
"type": "power_in",
"description": "3.3 V supply for the output 10 clock divider."
},
{
"number": "37",
"name": "OUT9",
"type": "output",
"description": "Square wave clocking output 9."
},
{
"number": "38",
"name": "~{OUT9}",
"type": "output",
"description": "Complementary square wave clocking output 9."
},
{
"number": "39",
"name": "VDD9",
"type": "power_in",
"description": "3.3 V supply for the output 9 clock driver."
},
{
"number": "40",
"name": "OUT8",
"type": "output",
"description": "Square wave clocking output 8."
},
{
"number": "41",
"name": "~{OUT8}",
"type": "output",
"description": "Complementary square wave clocking output 8."
},
{
"number": "42",
"name": "VDD8",
"type": "power_in",
"description": "3.3 V supply for the output 8 clock divider."
},
{
"number": "43",
"name": "OUT7",
"type": "output",
"description": "Square wave clocking output 7."
},
{
"number": "44",
"name": "~{OUT7}",
"type": "output",
"description": "Complementary square wave clocking output 7."
},
{
"number": "45",
"name": "VDD7",
"type": "power_in",
"description": "3.3 V supply for the output 7 clock driver."
},
{
"number": "46",
"name": "OUT6",
"type": "output",
"description": "Square wave clocking output 6."
},
{
"number": "47",
"name": "~{OUT6}",
"type": "output",
"description": "Complementary square wave clocking output 6."
},
{
"number": "48",
"name": "VDD6",
"type": "power_in",
"description": "3.3 V supply for the output 6 clock divider."
},
{
"number": "49",
"name": "OUT5",
"type": "output",
"description": "Square wave clocking output 5."
},
{
"number": "50",
"name": "~{OUT5}",
"type": "output",
"description": "Complementary square wave clocking output 5."
},
{
"number": "51",
"name": "VDD5",
"type": "power_in",
"description": "3.3 V supply for the output 5 clock driver."
},
{
"number": "52",
"name": "OUT4",
"type": "output",
"description": "Square wave clocking output 4."
},
{
"number": "53",
"name": "~{OUT4}",
"type": "output",
"description": "Complementary square wave clocking output 4."
},
{
"number": "54",
"name": "VDD4",
"type": "power_in",
"description": "3.3 V supply for the output 4 clock divider."
},
{
"number": "55",
"name": "STATUS0/SP0",
"type": "bidirectional",
"description": "Lock detect and other status signals / I2C address, with an internal 30 kΩ pull-down resistor."
},
{
"number": "56",
"name": "STATUS1/SP1",
"type": "bidirectional",
"description": "Lock detect and other status signals / I2C address, with an internal 30 kΩ pull-down resistor."
},
{
"number": "57",
"name": "SYSREF_REQ",
"type": "input",
"description": "SYSREF request input logic control."
},
{
"number": "58",
"name": "OUT3",
"type": "output",
"description": "Square wave clocking output 3."
},
{
"number": "59",
"name": "~{OUT3}",
"type": "output",
"description": "Complementary square wave clocking output 3; high speed output up to 1.25 GHz."
},
{
"number": "60",
"name": "VDD3",
"type": "power_in",
"description": "3.3 V supply for the output 3 clock driver; high speed output up to 1.25 GHz."
},
{
"number": "61",
"name": "OUT2",
"type": "output",
"description": "Square wave clocking output 2; high speed output up to 1.25 GHz."
},
{
"number": "62",
"name": "~{OUT2}",
"type": "output",
"description": "Complementary square wave clocking output 2; high speed output up to 1.25 GHz."
},
{
"number": "63",
"name": "VDD2",
"type": "power_in",
"description": "3.3 V supply for the output 2 clock divider."
},
{
"number": "64",
"name": "OUT1",
"type": "output",
"description": "Square wave clocking output 1; high speed output up to 1.25 GHz."
},
{
"number": "65",
"name": "~{OUT1}",
"type": "output",
"description": "Complementary square wave clocking output 1; high speed output up to 1.25 GHz."
},
{
"number": "66",
"name": "VDD1",
"type": "power_in",
"description": "3.3 V supply for the output 1 clock driver."
},
{
"number": "67",
"name": "OUT0",
"type": "output",
"description": "Square wave clocking output 0; high speed output up to 1.25 GHz."
},
{
"number": "68",
"name": "~{OUT0}",
"type": "output",
"description": "Complementary square wave clocking output 0; high speed output up to 1.25 GHz."
},
{
"number": "69",
"name": "VDD0",
"type": "power_in",
"description": "3.3 V supply for the output 0 clock divider."
},
{
"number": "70",
"name": "SYSREF_IN",
"type": "input",
"description": "External SYSREF input clock, differential with the complementary pin, or programmable as a single-ended 3.3 V CMOS input."
},
{
"number": "71",
"name": "~{SYSREF_IN}",
"type": "input",
"description": "Complementary external SYSREF input clock, differential with SYSREF_IN, or programmable as a single-ended 3.3 V CMOS input."
},
{
"number": "72",
"name": "VDD",
"type": "power_in",
"description": "3.3 V supply for the PLL1 input section."
},
{
"number": "73",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Overbars on complementary pin names were lost in the extracted text (e.g., REFA and its complement b; The Type column for CS (pin 21) is blank in the extracted table; classified as input from its descri; LDO_VCO is listed as P/O (power/output) decoupling pin; mapped to power_out. Verify."
],
"pages_sent": 20,
"cost_usd": 0.1951,
"at": "2026-11-09T06:18:17"
},
"datasheet": {
"url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD9528.pdf",
"pages": 68,
"sha256": "af314bce8f2f9fbc",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 73,
"described": 73,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad9528bcpz-reel7.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.02,
10.02,
0.9
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "7dcea6b62f9c762e1f3bcf79284fae5662898231dc6ab9c2030c0dd614e335f2",
"checked": "2026-11-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad9528bcpz-reel7-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
10.02,
10.02,
0.9
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "b37988986063e70e0f9bedd08feb9ec64619e6a25833abcb33a7cece0886e955",
"checked": "2026-11-09",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}