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AD9528BCPZ-REEL7

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Analog Devices Clock Generators / Frequency Synthesizers / PLL, LFCSP-72(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentclock and timingad9528bcpz-reel7factory-2.0.0extractor-text

Verified AD9528BCPZ-REEL7

by Ray · last 9 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

9 Nov 2026RayPublished by the parts factory: tier mfr, 73 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: AD9528BCPZ-REEL7 · LFCSP-72(10x10) · 73 pins
  • ✓copper: 73 copper pads, none touching another net
  • ✓datasheet: all 73 pin names found in the 68-page datasheet
  • ✓distributor: lcsc C481893, digikey 505-AD9528BCPZ-REEL7TR-ND, mouser 584-AD9528BCPZ-REEL7
  • ✓family: QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-b4g93jkf/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 73 pins = 73 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 73 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ ad9528bcpz-reel7.kicad_sym✓ ad9528bcpz-reel7.kicad_mod✓ ad9528bcpz-reel7.step
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Contents

README

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AD9528BCPZ-REEL7

Analog Devices · Clock Generators / Frequency Synthesizers / PLL · LFCSP-72(10x10)

AD9528BCPZ-REEL7 from Analog Devices, in a LFCSP-72(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in 3.3 V supply for the PLL1 input section.
2 REFA input Reference clock input A, differential with the complementary pin, or programmable as a single-ended 3.3 V CMOS input.
3 ~{REFA} input Complementary reference clock input A, differential with REFA, or programmable as a single-ended 3.3 V CMOS input.
4 REF_SEL input Reference input select; defaults to software control via Register 0x010A, Bits[2:0]; when the pin is active, logic low selects REFA and logic high selects REFB.
5 REFB input Reference clock input B, differential with the complementary pin, or programmable as a single-ended 3.3 V CMOS input.
6 ~{REFB} input Complementary reference clock input B, differential with REFB, or programmable as a single-ended 3.3 V CMOS input.
7 LF1 output PLL1 external loop filter connection.
8 VCXO_VT output VCXO control voltage; connect to the voltage control pin of the external VCXO.
9 NIC unconnected Not internally connected; can be left floating.
10 VDD power_in 3.3 V supply for the PLL2 section.
11 VCXO_IN input PLL1 oscillator input, differential with the complementary pin, or programmable as a single-ended 3.3 V CMOS input.
12 ~{VCXO_IN} input Complementary PLL1 oscillator input, differential with VCXO_IN, or programmable as a single-ended 3.3 V CMOS input.
13 NIC unconnected Not internally connected; can be left floating.
14 LF2_CAP output PLL2 external loop filter capacitor connection; connect a capacitor between this pin and the LDO_VCO pin.
15 LDO_VCO power_out 2.5 V LDO internal regulator decoupling for the VCO; connect a 0.47 µF capacitor to ground, placed close to the device.
16 VDD power_in 3.3 V supply for the PLL2 internal regulator.
17 NIC unconnected Not internally connected; can be left floating.
18 NIC unconnected Not internally connected; can be left floating.
19 RESET input Digital input, active low; resets internal logic to default states.
20 VDD power_in 3.3 V supply for the PLL2 internal regulator.
21 ~{CS} input Serial control port chip select, active low, with an internal 35 kΩ pull-up resistor.
22 SCLK/SCL input Serial control port clock for SPI mode (SCLK) or I2C mode (SCL); data clock for serial programming.
23 SDIO/SDA bidirectional Serial control port bidirectional data in/out for SPI mode (SDIO) or I2C mode (SDA).
24 SDO output Serial data output for reading data in 4-wire mode (high impedance in 3-wire mode); no internal pull-up or pull-down.
25 OUT13 output Square wave clocking output 13.
26 ~{OUT13} output Complementary square wave clocking output 13; high speed output up to 1.25 GHz.
27 VDD13 power_in 3.3 V supply for the output 13 clock driver; high speed output up to 1.25 GHz.
28 OUT12 output Square wave clocking output 12; high speed output up to 1.25 GHz.
29 ~{OUT12} output Complementary square wave clocking output 12; high speed output up to 1.25 GHz.
30 VDD12 power_in 3.3 V supply for the output 12 clock divider.
31 OUT11 output Square wave clocking output 11.
32 ~{OUT11} output Complementary square wave clocking output 11.
33 VDD11 power_in 3.3 V supply for the output 11 clock driver.
34 OUT10 output Square wave clocking output 10.
35 ~{OUT10} output Complementary square wave clocking output 10.
36 VDD10 power_in 3.3 V supply for the output 10 clock divider.
37 OUT9 output Square wave clocking output 9.
38 ~{OUT9} output Complementary square wave clocking output 9.
39 VDD9 power_in 3.3 V supply for the output 9 clock driver.
40 OUT8 output Square wave clocking output 8.
41 ~{OUT8} output Complementary square wave clocking output 8.
42 VDD8 power_in 3.3 V supply for the output 8 clock divider.
43 OUT7 output Square wave clocking output 7.
44 ~{OUT7} output Complementary square wave clocking output 7.
45 VDD7 power_in 3.3 V supply for the output 7 clock driver.
46 OUT6 output Square wave clocking output 6.
47 ~{OUT6} output Complementary square wave clocking output 6.
48 VDD6 power_in 3.3 V supply for the output 6 clock divider.
49 OUT5 output Square wave clocking output 5.
50 ~{OUT5} output Complementary square wave clocking output 5.
51 VDD5 power_in 3.3 V supply for the output 5 clock driver.
52 OUT4 output Square wave clocking output 4.
53 ~{OUT4} output Complementary square wave clocking output 4.
54 VDD4 power_in 3.3 V supply for the output 4 clock divider.
55 STATUS0/SP0 bidirectional Lock detect and other status signals / I2C address, with an internal 30 kΩ pull-down resistor.
56 STATUS1/SP1 bidirectional Lock detect and other status signals / I2C address, with an internal 30 kΩ pull-down resistor.
57 SYSREF_REQ input SYSREF request input logic control.
58 OUT3 output Square wave clocking output 3.
59 ~{OUT3} output Complementary square wave clocking output 3; high speed output up to 1.25 GHz.
60 VDD3 power_in 3.3 V supply for the output 3 clock driver; high speed output up to 1.25 GHz.
61 OUT2 output Square wave clocking output 2; high speed output up to 1.25 GHz.
62 ~{OUT2} output Complementary square wave clocking output 2; high speed output up to 1.25 GHz.
63 VDD2 power_in 3.3 V supply for the output 2 clock divider.
64 OUT1 output Square wave clocking output 1; high speed output up to 1.25 GHz.
65 ~{OUT1} output Complementary square wave clocking output 1; high speed output up to 1.25 GHz.
66 VDD1 power_in 3.3 V supply for the output 1 clock driver.
67 OUT0 output Square wave clocking output 0; high speed output up to 1.25 GHz.
68 ~{OUT0} output Complementary square wave clocking output 0; high speed output up to 1.25 GHz.
69 VDD0 power_in 3.3 V supply for the output 0 clock divider.
70 SYSREF_IN input External SYSREF input clock, differential with the complementary pin, or programmable as a single-ended 3.3 V CMOS input.
71 ~{SYSREF_IN} input Complementary external SYSREF input clock, differential with SYSREF_IN, or programmable as a single-ended 3.3 V CMOS input.
72 VDD power_in 3.3 V supply for the PLL1 input section.
73 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LFCSP-72(10x10)
Category Clock and Timing
Pins 73

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD VDD -0.3 3.6 V 16
REFA, REFA, REFB, REFB, VCXO_IN, VCXO_IN, SYSREF_IN, SYSREF_IN, SYSREF_REQ to GND -0.3 3.6 V to GND 16
SCLK/SCL, SDIO/SDA, SDO, CS to GND -0.3 3.6 V to GND 16
RESET, REF_SEL, SYSREF_REQ to GND -0.3 3.6 V to GND 16
STATUS0/SP0, STATUS1/SP1 to GND -0.3 3.6 V to GND 16
Junction temperature TJ 125 °C 16
Storage temperature range -65 150 °C 16
Lead temperature 300 °C 10 sec 16
Thermal resistance junction-to-ambient θJA 21.3 °C/W 72-lead LFCSP 10 mm × 10 mm, airflow 0 m/s 16
Thermal resistance junction-to-ambient θJA 20.1 °C/W 72-lead LFCSP 10 mm × 10 mm, airflow 1.0 m/s 16
Thermal resistance junction-to-ambient θJA 18.1 °C/W 72-lead LFCSP 10 mm × 10 mm, airflow 2.5 m/s 16
Thermal resistance junction-to-case θJC 1.7 °C/W 72-lead LFCSP 10 mm × 10 mm 16
Thermal resistance junction-to-board θJB 12.6 °C/W 72-lead LFCSP 10 mm × 10 mm 16
Junction-to-top characterization parameter ΨJT 0.1 °C/W 72-lead LFCSP 10 mm × 10 mm, airflow 0 m/s 16
Junction-to-top characterization parameter ΨJT 0.2 °C/W 72-lead LFCSP 10 mm × 10 mm, airflow 1.0 m/s 16
Junction-to-top characterization parameter ΨJT 0.3 °C/W 72-lead LFCSP 10 mm × 10 mm, airflow 2.5 m/s 16
Common-mode internally generated input voltage 0.6 0.7 0.8 V 6
Input common-mode range 0.4 1.4 V DC-coupled LVDS mode and HSTL mode supported 6
VCO frequency range 3450 4025 MHz 7
HSTL duty cycle 48 50 53 % f < 500 MHz 7
HSTL duty cycle 46 51 54 % f = 500 MHz to 800 MHz 7
HSTL duty cycle 44 50 62 % f = 800 MHz to 1.25 GHz 7
HSTL differential output voltage swing 900 1000 1100 mV VOH − VOL for each leg of a differential pair, default amplitude, driver not toggling 7
HSTL common-mode output voltage 0.88 0.9 0.94 V 7
LVDS duty cycle 47 50 53 % f < 500 MHz 8
LVDS duty cycle 46 51 54 % f = 500 MHz to 800 MHz 8
LVDS duty cycle 48 54 58 % f = 800 MHz to 1.25 GHz 8
Propagation latency of VCXO path 1.92 2.3 2.7 ns VCXO input to device clock output, not retimed 8
Propagation latency of SYSREF path 1.83 2.2 2.6 ns SYSREF input to SYSREF output, not retimed 8

CAD (KiCad official)

  • Symbol: AD9528BCPZ-REEL7
  • Footprint: Package_DFN_QFN:QFN-72-1EP_10x10mm_P0.5mm_EP6x6mm
  • 3D model: LFCSP-72(10x10) (KiCad packages3D, STEP)
  • 3D model files: ad9528bcpz-reel7-etched.step / ad9528bcpz-reel7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad9528bcpz-reel7.step / ad9528bcpz-reel7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (68 pp, sha256 af314bce8f2f9fbc, retrieved 2026-11-09, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF