AD7730BRZ-REEL7

{
  "slug": "ad7730brz-reel7",
  "version": "0.1.0",
  "type": "component",
  "description": "Analog Devices Analog To Digital Converters (ADCs), SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
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    "data converters",
    "ad7730brz-reel7",
    "factory-2.0.0",
    "extractor-text"
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  "component": {
    "mpn": "AD7730BRZ-REEL7",
    "manufacturer": "Analog Devices",
    "package": "SOIC-24-300mil",
    "pin_count": 24,
    "category": "Data Converters",
    "subcategory": "Analog To Digital Converters (ADCs)",
    "datasheet": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7730_7730L.pdf",
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      "lbr": "ad7730brz-reel7.lbr"
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    "distributor_links": {
      "lcsc": "C651493",
      "digikey": "AD7730BRZ-REEL7TR-ND",
      "mouser": "584-AD7730BRZ-R7"
    },
    "distributor_check": {
      "checked_at": "2026-10-28T15:49:30Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "AD7730BRZ-REEL7TR-ND",
        "status": "found"
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      "mouser": {
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    },
    "pins": [
      {
        "number": "1",
        "name": "SCLK",
        "type": "input",
        "description": "Schmitt-triggered serial clock input that transfers serial data to or from the AD7730, and it can be continuous or noncontinuous."
      },
      {
        "number": "2",
        "name": "MCLK IN",
        "type": "input",
        "description": "Master clock input that accepts a crystal/resonator or CMOS-compatible external clock, with the AD7730 specified at 4.9152 MHz."
      },
      {
        "number": "3",
        "name": "MCLK OUT",
        "type": "output",
        "description": "Crystal/resonator return output that provides an inverted clock when an external clock drives MCLK IN, and can drive one CMOS load; it can be turned off with the CLKDIS bit."
      },
      {
        "number": "4",
        "name": "POL",
        "type": "input",
        "description": "Logic input that sets the serial clock polarity, low for an active high-to-low SCLK edge and high for an active low-to-high SCLK edge."
      },
      {
        "number": "5",
        "name": "SYNC",
        "type": "input",
        "description": "Logic input that synchronizes the digital filters and analog modulators of multiple AD7730s, resetting the filter and calibration logic while held low."
      },
      {
        "number": "6",
        "name": "RESET",
        "type": "input",
        "description": "Active low logic input that resets the control logic, interface, digital filter, modulator and all on-chip registers to power-on status, except the clock oscillator."
      },
      {
        "number": "7",
        "name": "VBIAS",
        "type": "passive",
        "description": "Internally generated analog bias voltage that is not for external use, so nothing should be connected to this pin."
      },
      {
        "number": "8",
        "name": "AGND",
        "type": "power_in",
        "description": "Ground reference point for the analog circuitry."
      },
      {
        "number": "9",
        "name": "AVDD",
        "type": "power_in",
        "description": "Analog positive supply with 5 V nominal AVDD to AGND differential."
      },
      {
        "number": "10",
        "name": "AIN1(+)",
        "type": "passive",
        "description": "Positive input of the primary differential programmable-gain analog input pair, with ranges of 0 to +80 mV unipolar or ±80 mV bipolar."
      },
      {
        "number": "11",
        "name": "AIN1(–)",
        "type": "passive",
        "description": "Negative input of the primary differential programmable-gain analog input pair."
      },
      {
        "number": "12",
        "name": "AIN2(+)/D1",
        "type": "passive",
        "description": "Positive input of the secondary analog input pair or digital output bit D1, selected by the DEN bit of the Mode Register."
      },
      {
        "number": "13",
        "name": "AIN2(–)/D0",
        "type": "passive",
        "description": "Negative input of the secondary analog input pair or digital output bit D0, selected by the DEN bit of the Mode Register."
      },
      {
        "number": "14",
        "name": "REF IN(+)",
        "type": "input",
        "description": "Positive terminal of the differential reference input, which can lie anywhere between AVDD and AGND, with a nominal reference of +5 V when HIREF is 1 and +2.5 V when HIREF is 0."
      },
      {
        "number": "15",
        "name": "REF IN(–)",
        "type": "input",
        "description": "Negative terminal of the differential reference input, which can lie anywhere between AVDD and AGND."
      },
      {
        "number": "16",
        "name": "ACX",
        "type": "output",
        "description": "Digital output that controls reversal of the bridge excitation in ac-excited applications, held high when AC or CHP is 0."
      },
      {
        "number": "17",
        "name": "ACX",
        "type": "output",
        "description": "Digital output that is the complement of ACX, toggling in anti-phase with a nonoverlapping interval of one master clock cycle."
      },
      {
        "number": "18",
        "name": "STANDBY",
        "type": "input",
        "description": "Logic input that, when taken low, shuts down the analog and digital circuitry and reduces current consumption to the 5 μA range while retaining register values."
      },
      {
        "number": "19",
        "name": "CS",
        "type": "input",
        "description": "Active low chip select logic input used to select the AD7730 on a serial bus or as a frame synchronization signal."
      },
      {
        "number": "20",
        "name": "RDY",
        "type": "output",
        "description": "Status logic output that goes low to indicate a new output word is available in conversion mode and goes low at completion of calibration."
      },
      {
        "number": "21",
        "name": "DOUT",
        "type": "output",
        "description": "Serial data output from the output shift register containing calibration, mode, status, filter, DAC or data register contents selected by the Communications Register."
      },
      {
        "number": "22",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input that writes data to the input shift register, which transfers to the selected calibration, mode, communications, DAC or filter registers."
      },
      {
        "number": "23",
        "name": "DVDD",
        "type": "power_in",
        "description": "Digital supply voltage with +3 V or +5 V nominal."
      },
      {
        "number": "24",
        "name": "DGND",
        "type": "power_in",
        "description": "Ground reference point for the digital circuitry."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.3",
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        "factory": "2.0.0",
        "extractor": "extract_pins 0.3",
        "primary_model": "claude-haiku-5-5",
        "primary_mode": "text",
        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: The datasheet ordering guide lists AD7730BRZ-REEL7 in the 24-lead SOIC wide body package (RW-24), wh; The overbar on the complementary ACX output (pin 17) is lost in the extracted text, so both pins 16 ; The PIN CONFIGURATION diagram on page 7 is garbled in the extracted text, so pin positions were not "
        ],
        "pages_sent": 14,
        "cost_usd": 0.0402,
        "at": "2026-10-28T15:49:03"
      },
      "datasheet": {
        "url": "https://www.analog.com/media/en/technical-documentation/data-sheets/AD7730_7730L.pdf",
        "pages": 53,
        "sha256": "71122c870f1183b1",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 24,
        "described": 24,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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}