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AD7730BRZ-REEL7
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Analog Devices Analog To Digital Converters (ADCs), SOIC-24-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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Datasheet
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README
markdownAD7730BRZ-REEL7
Analog Devices · Analog To Digital Converters (ADCs) · SOIC-24-300mil
AD7730BRZ-REEL7 from Analog Devices, in a SOIC-24-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SCLK | input | Schmitt-triggered serial clock input that transfers serial data to or from the AD7730, and it can be continuous or noncontinuous. |
| 2 | MCLK IN | input | Master clock input that accepts a crystal/resonator or CMOS-compatible external clock, with the AD7730 specified at 4.9152 MHz. |
| 3 | MCLK OUT | output | Crystal/resonator return output that provides an inverted clock when an external clock drives MCLK IN, and can drive one CMOS load; it can be turned off with the CLKDIS bit. |
| 4 | POL | input | Logic input that sets the serial clock polarity, low for an active high-to-low SCLK edge and high for an active low-to-high SCLK edge. |
| 5 | SYNC | input | Logic input that synchronizes the digital filters and analog modulators of multiple AD7730s, resetting the filter and calibration logic while held low. |
| 6 | RESET | input | Active low logic input that resets the control logic, interface, digital filter, modulator and all on-chip registers to power-on status, except the clock oscillator. |
| 7 | VBIAS | passive | Internally generated analog bias voltage that is not for external use, so nothing should be connected to this pin. |
| 8 | AGND | power_in | Ground reference point for the analog circuitry. |
| 9 | AVDD | power_in | Analog positive supply with 5 V nominal AVDD to AGND differential. |
| 10 | AIN1(+) | passive | Positive input of the primary differential programmable-gain analog input pair, with ranges of 0 to +80 mV unipolar or ±80 mV bipolar. |
| 11 | AIN1(-) | passive | Negative input of the primary differential programmable-gain analog input pair. |
| 12 | AIN2(+)/D1 | passive | Positive input of the secondary analog input pair or digital output bit D1, selected by the DEN bit of the Mode Register. |
| 13 | AIN2(-)/D0 | passive | Negative input of the secondary analog input pair or digital output bit D0, selected by the DEN bit of the Mode Register. |
| 14 | REF IN(+) | input | Positive terminal of the differential reference input, which can lie anywhere between AVDD and AGND, with a nominal reference of +5 V when HIREF is 1 and +2.5 V when HIREF is 0. |
| 15 | REF IN(-) | input | Negative terminal of the differential reference input, which can lie anywhere between AVDD and AGND. |
| 16 | ACX | output | Digital output that controls reversal of the bridge excitation in ac-excited applications, held high when AC or CHP is 0. |
| 17 | ACX | output | Digital output that is the complement of ACX, toggling in anti-phase with a nonoverlapping interval of one master clock cycle. |
| 18 | STANDBY | input | Logic input that, when taken low, shuts down the analog and digital circuitry and reduces current consumption to the 5 μA range while retaining register values. |
| 19 | CS | input | Active low chip select logic input used to select the AD7730 on a serial bus or as a frame synchronization signal. |
| 20 | RDY | output | Status logic output that goes low to indicate a new output word is available in conversion mode and goes low at completion of calibration. |
| 21 | DOUT | output | Serial data output from the output shift register containing calibration, mode, status, filter, DAC or data register contents selected by the Communications Register. |
| 22 | DIN | input | Serial data input that writes data to the input shift register, which transfers to the selected calibration, mode, communications, DAC or filter registers. |
| 23 | DVDD | power_in | Digital supply voltage with +3 V or +5 V nominal. |
| 24 | DGND | power_in | Ground reference point for the digital circuitry. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Analog Devices |
| Package | SOIC-24-300mil |
| Category | Data Converters |
| Pins | 24 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| No Missing Codes | 24 | Bits | CHP = 1 | 2 | |||
| Integral Nonlinearity | 18 | ppm of FSR | CHP = 1 | 2 | |||
| Positive Full-Scale Drift vs Temp | 2 | ppm of FS/°C | CHP = 1 | 2 | |||
| Gain Drift vs. Temperature | 2 | ppm/°C | CHP = 1 | 2 | |||
| Negative Full-Scale Drift vs. Temp | 2 | ppm of FS/°C | CHP = 1 | 2 | |||
| Common-Mode Rejection (CMR) | 120 | dB | At DC. Measured with Zero Differential Voltage | 2 | |||
| Analog Input DC Bias Current | 50 | nA | CHP = 1 | 2 | |||
| Analog Input DC Offset Current | 10 | nA | CHP = 1 | 2 | |||
| Normal-Mode 50 Hz Rejection | 88 | dB | From 49 Hz to 51 Hz | 2 | |||
| Normal-Mode 60 Hz Rejection | 88 | dB | From 59 Hz to 61 Hz | 2 | |||
| Common-Mode 50 Hz Rejection | 120 | dB | From 49 Hz to 51 Hz | 2 | |||
| Common-Mode 60 Hz Rejection | 120 | dB | From 59 Hz to 61 Hz | 2 | |||
| Absolute/Common-Mode Voltage (min) | 1.2 | V | Printed as AGND + 1.2 V | 2 | |||
| Absolute/Common-Mode Voltage (max) | -0.95 | V | Printed as AVDD, 0.95 V | 2 | |||
| Reference Input Absolute/Common-Mode Voltage (min) | -30 | mV | Printed as AGND, 30 mV | 2 | |||
| Reference Input Absolute/Common-Mode Voltage (max) | 30 | mV | Printed as AVDD + 30 mV | 2 | |||
| NO REF Trigger Voltage (min) | VREF | 0.3 | V | NO REF Bit Active If VREF Below This Voltage | 2 | ||
| NO REF Trigger Voltage (max) | VREF | 0.65 | V | NO REF Bit Inactive If VREF Above This Voltage | 2 | ||
| Analog Input DC Bias Current | 60 | nA | CHP = 0 | 2 | |||
| Analog Input DC Offset Current | 30 | nA | CHP = 0 | 2 | |||
| Input Current | -10 | 10 | μA | All Inputs Except SCLK and MCLK IN | 3 | ||
| VINL, Input Low Voltage | VINL | 0.8 | V | DVDD = +5 V | 3 | ||
| VINL, Input Low Voltage | VINL | 0.4 | V | DVDD = +3 V | 3 | ||
| VINH, Input High Voltage | VINH | 2 | V | 3 | |||
| VINH, Input High Voltage (MCLK IN) | VINH | 3.5 | V | DVDD = +5 V | 3 | ||
| VINH, Input High Voltage (MCLK IN) | VINH | 2.5 | V | DVDD = +3 V | 3 | ||
| VINL, Input Low Voltage (MCLK IN) | VINL | 0.8 | V | DVDD = +5 V | 3 | ||
| VINL, Input Low Voltage (MCLK IN) | VINL | 0.4 | V | DVDD = +3 V | 3 | ||
| VOL, Output Low Voltage | VOL | 0.4 | V | ISINK = 800 μA; except MCLK OUT; VDD = +5 V | 3 | ||
| VOH, Output High Voltage | VOH | 4 | V | ISOURCE = 200 μA; except MCLK OUT; VDD = +5 V | 3 | ||
| Floating State Leakage Current | -10 | 10 | μA | 3 | |||
| LSB Size | 2.3 | 2.6 | mV | 2.5 mV nominal with 5 V reference (REF IN/2000) | 3 | ||
| DAC Drift | 2.5 | ppm/°C | 3 | ||||
| Differential Linearity | -0.25 | 0.75 | LSB | Guaranteed monotonic | 3 | ||
| Positive Full-Scale Calibration Limit | 1.05 | × FS V | FS is the nominal full-scale voltage (10 mV, 20 mV, 40 mV or 80 mV) | 3 | |||
| Negative Full-Scale Calibration Limit | -1.05 | × FS V | FS is the nominal full-scale voltage (10 mV, 20 mV, 40 mV or 80 mV) | 3 | |||
| Offset Calibration Limit | -1.05 | × FS V | 3 | ||||
| Input Span | 0.8 | 2.1 | × FS V | 3 | |||
| AVDD, AGND Voltage | AVDD | 4.75 | 5.25 | V | AVDD, AGND voltage | 3 | |
| DVDD Voltage | DVDD | 2.7 | 5.25 | V | With AGND = 0 V | 3 | |
| AVDD Current (Normal Mode) | AVDD | 10.3 | mA | All input ranges except 0 mV to +10 mV and ±10 mV | 3 | ||
| AVDD Current (Normal Mode) | AVDD | 22.3 | mA | Input ranges of 0 mV to +10 mV and ±10 mV only | 3 | ||
| DVDD Current (Normal Mode) | DVDD | 1.3 | mA | DVDD of 2.7 V to 3.3 V | 3 | ||
| DVDD Current (Normal Mode) | DVDD | 2.7 | mA | DVDD of 4.75 V to 5.25 V | 3 | ||
| AVDD + DVDD Current (Standby Mode) | 25 | μA | External MCLK IN = 0 V or DVDD | 3 | |||
| Power Dissipation (Normal Mode) | 65 | mW | AVDD = DVDD = +5 V; all input ranges except 0 mV to +10 mV and ±10 mV | 3 | |||
| Power Dissipation (Standby Mode) | 125 | μW | External MCLK IN = 0 V or DVDD | 3 | |||
| AVDD to AGND | -0.3 | 7 | V | 5 | |||
| AVDD to DGND | -0.3 | 7 | V | 5 | |||
| DVDD to AGND | -0.3 | 7 | V | 5 | |||
| Analog Input Voltage to AGND | -0.3 | V | Printed as -0.3 V to AVDD + 0.3 V | 5 | |||
| Reference Input Voltage to AGND | -0.3 | V | Printed as -0.3 V to AVDD + 0.3 V | 5 | |||
| AIN/REF IN Current | 30 | mA | Indefinite | 5 | |||
| Digital Input Voltage to DGND | -0.3 | V | Printed as -0.3 V to DVDD + 0.3 V | 5 | |||
| Operating Temperature Range | -40 | 85 | °C | Industrial (B Version) | 5 | ||
| θJA Thermal Impedance | θJA | 75 | °C/W | SOIC package | 5 |
CAD (KiCad official)
- Symbol:
AD7730BRZ-REEL7 - Footprint:
Package_SO:SOIC-24W_7.5x15.4mm_P1.27mm - 3D model: SOIC-24-300mil (KiCad packages3D, STEP)
- 3D model files:
ad7730brz-reel7-etched.step/ad7730brz-reel7-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ad7730brz-reel7.step/ad7730brz-reel7.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Analog Devices datasheet (53 pp, sha256
71122c870f1183b1, retrieved 2026-10-28, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).