AD7705BRZ-REEL

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  "slug": "ad7705brz-reel",
  "title": "AD7705BRZ-REEL",
  "brief": "Analog Devices Analog To Digital Converters (ADC), SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
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    "data acquisition",
    "ad7705brz-reel",
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  "component": {
    "mpn": "AD7705BRZ-REEL",
    "manufacturer": "Analog Devices",
    "package": "SOIC-16-300mil",
    "pin_count": 16,
    "category": "Data Acquisition",
    "subcategory": "Analog To Digital Converters (ADC)",
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      "lbr": "ad7705brz-reel.lbr"
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    "distributor_links": {
      "lcsc": "C9671",
      "digikey": "AD7705BRZ-REELTR-ND",
      "mouser": "584-AD7705BRZ-R"
    },
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        "pn": "AD7705BRZ-REELTR-ND",
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    },
    "pins": [
      {
        "number": "1",
        "name": "SCLK",
        "type": "input",
        "description": "Serial clock input on a Schmitt-triggered logic input that clocks serial data to and from the device, and may be continuous or non-continuous."
      },
      {
        "number": "2",
        "name": "MCLK IN",
        "type": "input",
        "description": "Master clock input that accepts a crystal/resonator across MCLK IN and MCLK OUT or a CMOS-compatible external clock, with the part operable from 500 kHz to 5 MHz."
      },
      {
        "number": "3",
        "name": "MCLK OUT",
        "type": "output",
        "description": "Inverted master clock output for external circuitry that is capable of driving 1 CMOS load and can be disabled via the CLKDIS bit of the clock register."
      },
      {
        "number": "4",
        "name": "CS",
        "type": "input",
        "description": "Active-low chip select that selects the device for communication, and can be hardwired low for 3-wire operation."
      },
      {
        "number": "5",
        "name": "RESET",
        "type": "input",
        "description": "Active-low reset input that returns the control logic, interface logic, calibration coefficients, digital filter and analog modulator to power-on status."
      },
      {
        "number": "6",
        "name": "AIN2(+)",
        "type": "input",
        "description": "Positive input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705."
      },
      {
        "number": "7",
        "name": "AIN1(+)",
        "type": "input",
        "description": "Positive input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705."
      },
      {
        "number": "8",
        "name": "AIN1(−)",
        "type": "input",
        "description": "Negative input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705."
      },
      {
        "number": "9",
        "name": "REF IN(+)",
        "type": "input",
        "description": "Positive differential reference input that must be greater than REF IN(-) and can lie anywhere between VDD and GND."
      },
      {
        "number": "10",
        "name": "REF IN(−)",
        "type": "input",
        "description": "Negative differential reference input that can lie anywhere between VDD and GND, provided REF IN(+) is greater than REF IN(-)."
      },
      {
        "number": "11",
        "name": "AIN2(−)",
        "type": "input",
        "description": "Negative input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705."
      },
      {
        "number": "12",
        "name": "DRDY",
        "type": "output",
        "description": "Logic output that goes low to indicate a new output word is available in the data register and also signals completion of on-chip calibration."
      },
      {
        "number": "13",
        "name": "DOUT",
        "type": "output",
        "description": "Serial data output from the output shift register, which holds the setup, communication, clock or data register contents selected by the communication register."
      },
      {
        "number": "14",
        "name": "DIN",
        "type": "input",
        "description": "Serial data input to the input shift register, which is transferred to the setup, clock or communication register as selected by the communication register."
      },
      {
        "number": "15",
        "name": "VDD",
        "type": "power_in",
        "description": "Supply voltage of 2.7 V to 5.25 V operation."
      },
      {
        "number": "16",
        "name": "GND",
        "type": "power_in",
        "description": "Ground reference point for the internal circuitry of the device."
      }
    ],
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        "primary_model": "claude-haiku-5-5",
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        "consensus_model": "claude-sonnet-5-5",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "extractor flagged: Pinout taken from the AD7705 column (Figure 3 pin configuration and Table 4 pin function description; Package mapping: the ordering guide lists AD7705BRZ-REEL (with footnote 1, Pb-free) as 16-Lead SOIC_"
        ],
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        "cost_usd": 0.0761,
        "at": "2026-10-19T02:22:51"
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        "total": 16,
        "described": 16,
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    "specs": {
      "Manufacturer": "Analog Devices",
      "Package": "SOIC-16-300mil",
      "Category": "Data Acquisition",
      "Pins": "16"
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          "name": "Power dissipation",
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          "name": "Master clock frequency fCLKIN",
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          "name": "Master clock input low time",
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          "name": "RESET pulse width",
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          "min": 100,
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        {
          "name": "DRDY to CS setup time",
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          "name": "CS falling edge to SCLK rising edge setup time (read)",
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          "name": "SCLK falling edge to data valid delay",
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          "name": "SCLK falling edge to data valid delay",
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          "name": "SCLK high pulse width (read)",
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          "name": "SCLK low pulse width (read)",
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          "name": "Bus relinquish time after SCLK rising edge",
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          "name": "Bus relinquish time after SCLK rising edge",
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          "name": "Bus relinquish time after SCLK rising edge",
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          "name": "SCLK falling edge to DRDY high",
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          "typ": null,
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        {
          "name": "Data valid to SCLK rising edge hold time",
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          "kind": "timing",
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          "min": 20,
          "typ": null,
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          "source_page": 8,
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          "name": "SCLK high pulse width (write)",
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          "kind": "timing",
          "unit": "ns",
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          "source_page": 8,
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          "name": "SCLK low pulse width (write)",
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          "kind": "timing",
          "unit": "ns",
          "min": 100,
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          "source_page": 8,
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        {
          "name": "CS rising edge to SCLK rising edge hold time (write)",
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        {
          "name": "MCLK IN clock frequency range",
          "symbol": "",
          "kind": "recommended_operating",
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          "typ": null,
          "max": null,
          "conditions": "Pin description: operated with clock frequencies in the range of 500 kHz to 5 MHz",
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        {
          "name": "MCLK IN clock frequency range",
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          "conditions": "Pin description: operated with clock frequencies in the range of 500 kHz to 5 MHz",
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        {
          "name": "VDD to GND",
          "symbol": "VDD",
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          "unit": "V",
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          "typ": null,
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          "conditions": "To GND",
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        {
          "name": "Analog Input Voltage to GND",
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          "kind": "absolute_maximum",
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          "conditions": "To GND; upper limit printed as VDD + 0.3 V (not numeric)",
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        {
          "name": "Reference Input Voltage to GND",
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          "typ": null,
          "max": null,
          "conditions": "To GND; upper limit printed as VDD + 0.3 V (not numeric)",
          "source_page": 9,
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