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AD7705BRZ-REEL

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Analog Devices Analog To Digital Converters (ADC), SOIC-16-300mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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AD7705BRZ-REEL

Analog Devices · Analog To Digital Converters (ADC) · SOIC-16-300mil

AD7705BRZ-REEL from Analog Devices, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SCLK input Serial clock input on a Schmitt-triggered logic input that clocks serial data to and from the device, and may be continuous or non-continuous.
2 MCLK IN input Master clock input that accepts a crystal/resonator across MCLK IN and MCLK OUT or a CMOS-compatible external clock, with the part operable from 500 kHz to 5 MHz.
3 MCLK OUT output Inverted master clock output for external circuitry that is capable of driving 1 CMOS load and can be disabled via the CLKDIS bit of the clock register.
4 CS input Active-low chip select that selects the device for communication, and can be hardwired low for 3-wire operation.
5 RESET input Active-low reset input that returns the control logic, interface logic, calibration coefficients, digital filter and analog modulator to power-on status.
6 AIN2(+) input Positive input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705.
7 AIN1(+) input Positive input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705.
8 AIN1(−) input Negative input of the differential analog input pair AIN1(+)/AIN1(-) on the AD7705.
9 REF IN(+) input Positive differential reference input that must be greater than REF IN(-) and can lie anywhere between VDD and GND.
10 REF IN(−) input Negative differential reference input that can lie anywhere between VDD and GND, provided REF IN(+) is greater than REF IN(-).
11 AIN2(−) input Negative input of the differential analog input pair AIN2(+)/AIN2(-) on the AD7705.
12 DRDY output Logic output that goes low to indicate a new output word is available in the data register and also signals completion of on-chip calibration.
13 DOUT output Serial data output from the output shift register, which holds the setup, communication, clock or data register contents selected by the communication register.
14 DIN input Serial data input to the input shift register, which is transferred to the setup, clock or communication register as selected by the communication register.
15 VDD power_in Supply voltage of 2.7 V to 5.25 V operation.
16 GND power_in Ground reference point for the internal circuitry of the device.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package SOIC-16-300mil
Category Data Acquisition
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD Voltage (3 V operation) VDD 2.7 3.3 V For specified performance 7
VDD Voltage (5 V operation) VDD 4.75 5.25 V For specified performance 7
Power Supply Current 0.32 mA VDD 2.7-3.3 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 0, fCLKIN = 1 MHz, gains 1 to 128 7
Power Supply Current 0.6 mA VDD 2.7-3.3 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 1, fCLKIN = 1 MHz, gains 1 to 128 7
Power Supply Current 0.4 mA VDD 2.7-3.3 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 0, fCLKIN = 2.4576 MHz, gains 1 to 4 7
Power Supply Current 0.7 mA VDD 2.7-3.3 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 1, fCLKIN = 2.4576 MHz, gains 1 to 4 7
Power Supply Current 1.1 mA VDD 2.7-3.3 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 1, fCLKIN = 2.4576 MHz, gains 8 to 128 7
Power Supply Current 0.45 mA VDD 4.75-5.25 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 0, fCLKIN = 1 MHz, gains 1 to 128 7
Power Supply Current 0.85 mA VDD 4.75-5.25 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 0, fCLKIN = 2.4576 MHz, gains 8 to 128 7
Power Supply Current 0.9 mA VDD 4.75-5.25 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 1, fCLKIN = 2.4576 MHz, gains 1 to 4 7
Power Supply Current 1.3 mA VDD 4.75-5.25 V; digital I/Ps = 0 V or VDD; external MCLK IN, CLKDIS = 1; BUF bit = 1, fCLKIN = 2.4576 MHz, gains 8 to 128 7
Standby (Power-Down) Current 16 μA VDD = 5 V; external MCLK IN = 0 V or VDD 7
Standby (Power-Down) Current 8 μA VDD = 3 V; external MCLK IN = 0 V or VDD 7
Analog input voltage (absolute, for specified performance) -100 mV Absolute voltage on analog inputs for specified performance; upper limit is VDD + 30 mV (not numeric) 7
Power dissipation 1 mW VDD = 3 V 1
Master clock frequency fCLKIN fCLKIN 400 kHz Master clock frequency (crystal oscillator or externally supplied) 8
Master clock frequency fCLKIN fCLKIN 2.5 MHz For specified performance 8
fCLKIN duty cycle fCLKIN 45 55 % Duty cycle range 8
Master clock input low time tCLKIN LO 0.4 × tCLKIN ns tCLKIN = 1/fCLKIN 8
Master clock input high time tCLKIN HI 0.4 × tCLKIN ns 8
RESET pulse width t2 100 ns 8
DRDY to CS setup time t3 0 ns 8
CS falling edge to SCLK rising edge setup time (read) t4 120 ns 8
SCLK falling edge to data valid delay t5 0 ns 8
SCLK falling edge to data valid delay t5 80 ns VDD = 5 V 8
SCLK falling edge to data valid delay t5 100 ns VDD = 3.0 V 8
SCLK high pulse width (read) t6 100 ns 8
SCLK low pulse width (read) t7 100 ns 8
CS rising edge to SCLK rising edge hold time (read) t8 0 ns 8
Bus relinquish time after SCLK rising edge t9 10 ns 8
Bus relinquish time after SCLK rising edge t9 60 ns VDD = 5 V 8
Bus relinquish time after SCLK rising edge t9 100 ns VDD = 3.0 V 8
SCLK falling edge to DRDY high t10 100 ns 8
CS falling edge to SCLK rising edge setup time (write) t11 120 ns 8
Data valid to SCLK rising edge setup time t12 30 ns 8
Data valid to SCLK rising edge hold time t13 20 ns 8
SCLK high pulse width (write) t14 100 ns 8
SCLK low pulse width (write) t15 100 ns 8
CS rising edge to SCLK rising edge hold time (write) t16 0 ns 8
MCLK IN clock frequency range 500 kHz Pin description: operated with clock frequencies in the range of 500 kHz to 5 MHz 10
MCLK IN clock frequency range 5 MHz Pin description: operated with clock frequencies in the range of 500 kHz to 5 MHz 10
VDD to GND VDD -0.3 7 V To GND 9
Analog Input Voltage to GND -0.3 V To GND; upper limit printed as VDD + 0.3 V (not numeric) 9
Reference Input Voltage to GND -0.3 V To GND; upper limit printed as VDD + 0.3 V (not numeric) 9
Digital Input Voltage to GND -0.3 V To GND; upper limit printed as VDD + 0.3 V (not numeric) 9
Digital Output Voltage to GND -0.3 V To GND; upper limit printed as VDD + 0.3 V (not numeric) 9
Operating Temperature Range (Commercial, B Version) -40 85 °C 9
Storage Temperature Range -65 150 °C 9
Junction Temperature 150 °C 9
Power Dissipation (SOIC package) 450 mW SOIC package 9
θJA Thermal Impedance (SOIC package) θJA 75 °C/W SOIC package 9
Lead Temperature, Soldering, Vapor Phase (60 sec) 215 °C SOIC package, vapor phase, 60 sec 9
Lead Temperature, Soldering, Infrared (15 sec) 220 °C SOIC package, infrared, 15 sec 9
ESD Rating 4000 V Printed as >4000 V 9
Reference input DC leakage current -1 1 nA Maximum dc input leakage over temperature, REF IN(+) and REF IN(−) 23
Latch-up current 100 mA Printed as greater than 100 mA 30

CAD (KiCad official)

  • Symbol: AD7705BRZ-REEL
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
  • 3D model files: ad7705brz-reel-etched.step / ad7705brz-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7705brz-reel.step / ad7705brz-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (44 pp, sha256 822cb538aa5c64e3, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF