component
AD7616BSTZ-RL
Public Made by Adomby adom
Analog Devices Analog To Digital Converters (ADC), LQFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "ad7616bstz-rl",
"version": "0.1.0",
"type": "component",
"description": "Analog Devices Analog To Digital Converters (ADC), LQFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"data acquisition",
"ad7616bstz-rl",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
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"ad7616bstz-rl.step",
"ad7616bstz-rl.lbr",
"docs/hero.png",
"docs/ad7616bstz-rl-datasheet.pdf",
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"ad7616bstz-rl-hero.glb",
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"ad7616bstz-rl-etched.glb"
],
"component": {
"mpn": "AD7616BSTZ-RL",
"manufacturer": "Analog Devices",
"package": "LQFP-80(14x14)",
"pin_count": 80,
"category": "Data Acquisition",
"subcategory": "Analog To Digital Converters (ADC)",
"datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885977092009984",
"parts": {
"symbol": "ad7616bstz-rl.kicad_sym",
"footprint": "ad7616bstz-rl.kicad_mod",
"model_3d": "ad7616bstz-rl-hero.glb",
"model_3d_plain": "ad7616bstz-rl-etched.glb",
"model_3d_step": "ad7616bstz-rl-etched.step",
"model_3d_step_plain": "ad7616bstz-rl.step",
"lbr": "ad7616bstz-rl.lbr"
},
"distributor_links": {
"lcsc": "C651298",
"digikey": "505-AD7616BSTZ-RLTR-ND",
"mouser": "584-AD7616BSTZ-RL"
},
"distributor_check": {
"checked_at": "2026-10-17T20:47:59Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "505-AD7616BSTZ-RLTR-ND",
"status": "found"
},
"mouser": {
"pn": "584-AD7616BSTZ-RL",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "V4BGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V4B (ADC B, channel 4)."
},
{
"number": "2",
"name": "V4B",
"type": "input",
"description": "Analog input for channel 4 on ADC B."
},
{
"number": "3",
"name": "V5BGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V5B (ADC B, channel 5)."
},
{
"number": "4",
"name": "V5B",
"type": "input",
"description": "Analog input for channel 5 on ADC B."
},
{
"number": "5",
"name": "AGND",
"type": "power_in",
"description": "Analog supply ground pin."
},
{
"number": "6",
"name": "VCC",
"type": "power_in",
"description": "Analog supply voltage, 4.7 V to 5.25 V, applied to the front-end amplifiers and ADC core; decouple to AGND with 0.1 µF and 10 µF capacitors in parallel."
},
{
"number": "7",
"name": "V6B",
"type": "input",
"description": "Analog input for channel 6 on ADC B."
},
{
"number": "8",
"name": "V6BGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V6B."
},
{
"number": "9",
"name": "V7B",
"type": "input",
"description": "Analog input for channel 7 on ADC B."
},
{
"number": "10",
"name": "V7BGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V7B."
},
{
"number": "11",
"name": "V7AGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V7A."
},
{
"number": "12",
"name": "V7A",
"type": "input",
"description": "Analog input for channel 7 on ADC A."
},
{
"number": "13",
"name": "V6AGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V6A."
},
{
"number": "14",
"name": "V6A",
"type": "input",
"description": "Analog input for channel 6 on ADC A."
},
{
"number": "15",
"name": "VCC",
"type": "power_in",
"description": "Analog supply voltage, 4.7 V to 5.25 V, applied to the front-end amplifiers and ADC core; decouple to AGND with 0.1 µF and 10 µF capacitors in parallel."
},
{
"number": "16",
"name": "AGND",
"type": "power_in",
"description": "Analog supply ground pin."
},
{
"number": "17",
"name": "V5A",
"type": "input",
"description": "Analog input for channel 5 on ADC A, referenced to V5AGND (pin 18)."
},
{
"number": "18",
"name": "V5AGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V5A."
},
{
"number": "19",
"name": "V4A",
"type": "input",
"description": "Analog input for channel 4 on ADC A, referenced to V4AGND (pin 20)."
},
{
"number": "20",
"name": "V4AGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V4A."
},
{
"number": "21",
"name": "V3AGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V3A."
},
{
"number": "22",
"name": "V3A",
"type": "input",
"description": "Analog input for channel 3 on ADC A."
},
{
"number": "23",
"name": "V2AGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V2A."
},
{
"number": "24",
"name": "V2A",
"type": "input",
"description": "Analog input for channel 2 on ADC A."
},
{
"number": "25",
"name": "V1AGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V1A."
},
{
"number": "26",
"name": "V1A",
"type": "input",
"description": "Analog input for channel 1 on ADC A."
},
{
"number": "27",
"name": "V0AGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V0A."
},
{
"number": "28",
"name": "V0A",
"type": "input",
"description": "Analog input for channel 0 on ADC A."
},
{
"number": "29",
"name": "AGND",
"type": "power_in",
"description": "Analog supply ground pin."
},
{
"number": "30",
"name": "VCC",
"type": "power_in",
"description": "Analog supply voltage, 4.7 V to 5.25 V, applied to the front-end amplifiers and ADC core; decouple to AGND with 0.1 µF and 10 µF capacitors in parallel."
},
{
"number": "31",
"name": "REFCAP",
"type": "passive",
"description": "Reference buffer output force/sense pin; decouple to AGND with a low-ESR 10 µF X5R ceramic capacitor placed as close as possible, typically 4.096 V."
},
{
"number": "32",
"name": "REFGND",
"type": "power_in",
"description": "Reference ground pin; connect to AGND."
},
{
"number": "33",
"name": "REFINOUT",
"type": "bidirectional",
"description": "Reference input/output: provides the 2.5 V internal reference when REFSEL is high, or accepts a 2.5 V external reference when REFSEL is low; requires a 100 nF X8R decoupling capacitor to REFINOUTGND and a 10 kΩ series resistor if an external reference is used."
},
{
"number": "34",
"name": "REFINOUTGND",
"type": "power_in",
"description": "Reference input/output ground pin for REFINOUT."
},
{
"number": "35",
"name": "REFSEL",
"type": "input",
"description": "Logic input selecting the internal reference (high) or external reference (low); latched on release of a full reset."
},
{
"number": "36",
"name": "RESET",
"type": "input",
"description": "Reset input: a 40 ns to 500 ns low pulse gives a partial reset, a low pulse of at least 1.2 µs gives a full reset, and holding it low places the device in shutdown."
},
{
"number": "37",
"name": "SEQEN",
"type": "input",
"description": "Channel sequencer enable in hardware mode; low disables the sequencer, and it must be tied to DGND in software mode; latched on release of a full reset."
},
{
"number": "38",
"name": "HW_RNGSEL1",
"type": "input",
"description": "Hardware/software mode select (latched at full reset) and hardware-mode range select bit 1 (00 = software mode, 01 = ±2.5 V, 10 = ±5 V, 11 = ±10 V)."
},
{
"number": "39",
"name": "HW_RNGSEL0",
"type": "input",
"description": "Hardware/software mode select (latched at full reset) and hardware-mode range select bit 0 (00 = software mode, 01 = ±2.5 V, 10 = ±5 V, 11 = ±10 V)."
},
{
"number": "40",
"name": "SER/PAR",
"type": "input",
"description": "Serial/parallel interface select: low selects the parallel interface and high selects the serial interface; latched on release of a full reset."
},
{
"number": "41",
"name": "DB0",
"type": "bidirectional",
"description": "Parallel data bit 0 (output/input); must be tied to DGND in serial mode."
},
{
"number": "42",
"name": "DB1",
"type": "bidirectional",
"description": "Parallel data bit 1 (output/input); must be tied to DGND in serial mode."
},
{
"number": "43",
"name": "DB2",
"type": "bidirectional",
"description": "Parallel data bit 2 (output/input); must be tied to DGND in serial mode."
},
{
"number": "44",
"name": "DB3",
"type": "bidirectional",
"description": "Parallel data bit 3 (output/input); must be tied to DGND in serial mode."
},
{
"number": "45",
"name": "DB4/SER1W",
"type": "bidirectional",
"description": "Parallel data bit 4 (three-state output/input) in parallel mode; in serial mode selects SDOA-only (low) or SDOA and SDOB (high) output, latched on full reset."
},
{
"number": "46",
"name": "DB5/CRCEN",
"type": "bidirectional",
"description": "Parallel data bit 5 in parallel mode; in serial mode, CRC enable input (high adds a CRC word after the conversion words), latched on full reset."
},
{
"number": "47",
"name": "DB6",
"type": "bidirectional",
"description": "Parallel data bit 6 (three-state input/output) when SER/PAR = 0; tie to DGND in serial mode."
},
{
"number": "48",
"name": "DB7",
"type": "bidirectional",
"description": "Parallel data bit 7 (three-state input/output) when SER/PAR = 0; tie to DGND in serial mode."
},
{
"number": "49",
"name": "VDRIVE",
"type": "power_in",
"description": "Logic power supply input, 2.3 V to 3.6 V, setting the interface voltage; decouple with 0.1 µF and 10 µF capacitors in parallel."
},
{
"number": "50",
"name": "DGND",
"type": "power_in",
"description": "Digital ground, the ground reference for all digital circuitry; connect to the system digital ground plane."
},
{
"number": "51",
"name": "REGGNDD",
"type": "power_in",
"description": "Ground for the digital LDO regulator connected to REGCAPD (pin 52)."
},
{
"number": "52",
"name": "REGCAPD",
"type": "power_out",
"description": "Decoupling pin for the internal digital regulator output, typically 1.89 V; decouple to REGGNDD with a 10 µF capacitor."
},
{
"number": "53",
"name": "DB8",
"type": "bidirectional",
"description": "Parallel data bit 8 (three-state input/output) when SER/PAR = 0; tie to DGND in serial mode."
},
{
"number": "54",
"name": "DB9",
"type": "bidirectional",
"description": "Parallel data bit 9 (three-state input/output) when SER/PAR = 0; tie to DGND in serial mode."
},
{
"number": "55",
"name": "DB10/SDI",
"type": "bidirectional",
"description": "Parallel data bit 10 when SER/PAR = 0; serial data input of the SPI interface in serial mode (tie to DGND in hardware serial mode)."
},
{
"number": "56",
"name": "DB11/SDOB",
"type": "bidirectional",
"description": "Parallel data bit 11 when SER/PAR = 0; serial data output B in serial mode."
},
{
"number": "57",
"name": "DB12/SDOA",
"type": "bidirectional",
"description": "Parallel data bit 12 when SER/PAR = 0; serial data output A in serial mode."
},
{
"number": "58",
"name": "DB13/OS0",
"type": "bidirectional",
"description": "Parallel data bit 13 when SER/PAR = 0; oversampling ratio select OS0 in hardware serial mode, latched on full reset."
},
{
"number": "59",
"name": "DB14/OS1",
"type": "bidirectional",
"description": "Parallel data bit 14 when SER/PAR = 0; oversampling ratio select OS1 in hardware serial mode, latched on full reset."
},
{
"number": "60",
"name": "DB15/OS2",
"type": "bidirectional",
"description": "Parallel data bit 15 when SER/PAR = 0; oversampling ratio select OS2 in hardware serial mode, latched on full reset."
},
{
"number": "61",
"name": "WR/BURST",
"type": "input",
"description": "Write strobe in software parallel mode; burst mode enable in hardware mode, latched on full reset; connect to DGND in software serial mode."
},
{
"number": "62",
"name": "SCLK/RD",
"type": "input",
"description": "Serial clock input in serial mode; parallel read control (active low with CS) in parallel mode."
},
{
"number": "63",
"name": "CS",
"type": "input",
"description": "Active-low chip select that frames data transfers; in parallel mode with RD low it enables the DBx output bus."
},
{
"number": "64",
"name": "CHSEL0",
"type": "input",
"description": "Channel selection input bit 0 for hardware-mode channel pair selection (must be stable before CONVST rising edge); tie to DGND in software mode."
},
{
"number": "65",
"name": "CHSEL1",
"type": "input",
"description": "Channel selection input bit 1 for hardware-mode channel pair selection (must be stable before CONVST rising edge); tie to DGND in software mode."
},
{
"number": "66",
"name": "CHSEL2",
"type": "input",
"description": "Channel selection input bit 2 for hardware-mode channel pair selection (must be stable before CONVST rising edge); tie to DGND in software mode."
},
{
"number": "67",
"name": "BUSY",
"type": "output",
"description": "Busy output that goes high after a CONVST rising edge and returns low when conversion data is ready to read; read data only after BUSY is low."
},
{
"number": "68",
"name": "CONVST",
"type": "input",
"description": "Conversion start input for channel groups A and B; a low-to-high transition initiates conversion of the selected channel pair(s)."
},
{
"number": "69",
"name": "REGGND",
"type": "power_in",
"description": "Internal analog regulator ground; must connect to the system AGND plane."
},
{
"number": "70",
"name": "REGCAP",
"type": "power_out",
"description": "Decoupling pin for the internal analog regulator output, typically 1.87 V; decouple to REGGND with a 10 µF capacitor."
},
{
"number": "71",
"name": "VCC",
"type": "power_in",
"description": "Analog supply voltage, 4.7 V to 5.25 V, applied to the front-end amplifiers and ADC core; decouple to AGND with 0.1 µF and 10 µF capacitors in parallel."
},
{
"number": "72",
"name": "AGND",
"type": "power_in",
"description": "Analog supply ground pin."
},
{
"number": "73",
"name": "V0B",
"type": "input",
"description": "Analog input for channel 0 on ADC B."
},
{
"number": "74",
"name": "V0BGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V0B."
},
{
"number": "75",
"name": "V1B",
"type": "input",
"description": "Analog input for channel 1 on ADC B."
},
{
"number": "76",
"name": "V1BGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V1B."
},
{
"number": "77",
"name": "V2B",
"type": "input",
"description": "Analog input for channel 2 on ADC B."
},
{
"number": "78",
"name": "V2BGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V2B."
},
{
"number": "79",
"name": "V3B",
"type": "input",
"description": "Analog input for channel 3 on ADC B."
},
{
"number": "80",
"name": "V3BGND",
"type": "power_in",
"description": "Analog input ground pin for analog input V3B."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Package variant confirmed: the Ordering Guide (page 50) lists AD7616BSTZ-RL as 80-lead LQFP, ST-80-2; Pins 53 and 54 are listed as 'DB8, DB9' in Table 7 with the description order reversed ('Data Bit 9 ; Pin 17 (V5A), pin 19 (V4A) and the other ADC A/B analog inputs are only described as 'Analog Input V"
],
"pages_sent": 14,
"cost_usd": 0.1478,
"at": "2026-10-17T20:45:35"
},
"datasheet": {
"url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588885977092009984",
"pages": 50,
"sha256": "1c8b73c9521cdb33",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 80,
"described": 80,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "ad7616bstz-rl.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
16.4,
16.4,
1.6
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "477979184005b1973cf4f2ae93e03c5a50342504190416921945164d4f1db58d",
"checked": "2026-10-17",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "ad7616bstz-rl-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
16.4,
16.4,
1.6
],
"zmin_mm": -0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "76a56b1377bf7cf232a313b9fb649029f15d6b7dcb429f6514f8e826a0260119",
"checked": "2026-10-17",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}