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AD7616BSTZ-RL

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Analog Devices Analog To Digital Converters (ADC), LQFP-80(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

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AD7616BSTZ-RL

Analog Devices · Analog To Digital Converters (ADC) · LQFP-80(14x14)

AD7616BSTZ-RL from Analog Devices, in a LQFP-80(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 V4BGND power_in Analog input ground pin for analog input V4B (ADC B, channel 4).
2 V4B input Analog input for channel 4 on ADC B.
3 V5BGND power_in Analog input ground pin for analog input V5B (ADC B, channel 5).
4 V5B input Analog input for channel 5 on ADC B.
5 AGND power_in Analog supply ground pin.
6 VCC power_in Analog supply voltage, 4.7 V to 5.25 V, applied to the front-end amplifiers and ADC core; decouple to AGND with 0.1 µF and 10 µF capacitors in parallel.
7 V6B input Analog input for channel 6 on ADC B.
8 V6BGND power_in Analog input ground pin for analog input V6B.
9 V7B input Analog input for channel 7 on ADC B.
10 V7BGND power_in Analog input ground pin for analog input V7B.
11 V7AGND power_in Analog input ground pin for analog input V7A.
12 V7A input Analog input for channel 7 on ADC A.
13 V6AGND power_in Analog input ground pin for analog input V6A.
14 V6A input Analog input for channel 6 on ADC A.
15 VCC power_in Analog supply voltage, 4.7 V to 5.25 V, applied to the front-end amplifiers and ADC core; decouple to AGND with 0.1 µF and 10 µF capacitors in parallel.
16 AGND power_in Analog supply ground pin.
17 V5A input Analog input for channel 5 on ADC A, referenced to V5AGND (pin 18).
18 V5AGND power_in Analog input ground pin for analog input V5A.
19 V4A input Analog input for channel 4 on ADC A, referenced to V4AGND (pin 20).
20 V4AGND power_in Analog input ground pin for analog input V4A.
21 V3AGND power_in Analog input ground pin for analog input V3A.
22 V3A input Analog input for channel 3 on ADC A.
23 V2AGND power_in Analog input ground pin for analog input V2A.
24 V2A input Analog input for channel 2 on ADC A.
25 V1AGND power_in Analog input ground pin for analog input V1A.
26 V1A input Analog input for channel 1 on ADC A.
27 V0AGND power_in Analog input ground pin for analog input V0A.
28 V0A input Analog input for channel 0 on ADC A.
29 AGND power_in Analog supply ground pin.
30 VCC power_in Analog supply voltage, 4.7 V to 5.25 V, applied to the front-end amplifiers and ADC core; decouple to AGND with 0.1 µF and 10 µF capacitors in parallel.
31 REFCAP passive Reference buffer output force/sense pin; decouple to AGND with a low-ESR 10 µF X5R ceramic capacitor placed as close as possible, typically 4.096 V.
32 REFGND power_in Reference ground pin; connect to AGND.
33 REFINOUT bidirectional Reference input/output: provides the 2.5 V internal reference when REFSEL is high, or accepts a 2.5 V external reference when REFSEL is low; requires a 100 nF X8R decoupling capacitor to REFINOUTGND and a 10 kΩ series resistor if an external reference is used.
34 REFINOUTGND power_in Reference input/output ground pin for REFINOUT.
35 REFSEL input Logic input selecting the internal reference (high) or external reference (low); latched on release of a full reset.
36 RESET input Reset input: a 40 ns to 500 ns low pulse gives a partial reset, a low pulse of at least 1.2 µs gives a full reset, and holding it low places the device in shutdown.
37 SEQEN input Channel sequencer enable in hardware mode; low disables the sequencer, and it must be tied to DGND in software mode; latched on release of a full reset.
38 HW_RNGSEL1 input Hardware/software mode select (latched at full reset) and hardware-mode range select bit 1 (00 = software mode, 01 = ±2.5 V, 10 = ±5 V, 11 = ±10 V).
39 HW_RNGSEL0 input Hardware/software mode select (latched at full reset) and hardware-mode range select bit 0 (00 = software mode, 01 = ±2.5 V, 10 = ±5 V, 11 = ±10 V).
40 SER/PAR input Serial/parallel interface select: low selects the parallel interface and high selects the serial interface; latched on release of a full reset.
41 DB0 bidirectional Parallel data bit 0 (output/input); must be tied to DGND in serial mode.
42 DB1 bidirectional Parallel data bit 1 (output/input); must be tied to DGND in serial mode.
43 DB2 bidirectional Parallel data bit 2 (output/input); must be tied to DGND in serial mode.
44 DB3 bidirectional Parallel data bit 3 (output/input); must be tied to DGND in serial mode.
45 DB4/SER1W bidirectional Parallel data bit 4 (three-state output/input) in parallel mode; in serial mode selects SDOA-only (low) or SDOA and SDOB (high) output, latched on full reset.
46 DB5/CRCEN bidirectional Parallel data bit 5 in parallel mode; in serial mode, CRC enable input (high adds a CRC word after the conversion words), latched on full reset.
47 DB6 bidirectional Parallel data bit 6 (three-state input/output) when SER/PAR = 0; tie to DGND in serial mode.
48 DB7 bidirectional Parallel data bit 7 (three-state input/output) when SER/PAR = 0; tie to DGND in serial mode.
49 VDRIVE power_in Logic power supply input, 2.3 V to 3.6 V, setting the interface voltage; decouple with 0.1 µF and 10 µF capacitors in parallel.
50 DGND power_in Digital ground, the ground reference for all digital circuitry; connect to the system digital ground plane.
51 REGGNDD power_in Ground for the digital LDO regulator connected to REGCAPD (pin 52).
52 REGCAPD power_out Decoupling pin for the internal digital regulator output, typically 1.89 V; decouple to REGGNDD with a 10 µF capacitor.
53 DB8 bidirectional Parallel data bit 8 (three-state input/output) when SER/PAR = 0; tie to DGND in serial mode.
54 DB9 bidirectional Parallel data bit 9 (three-state input/output) when SER/PAR = 0; tie to DGND in serial mode.
55 DB10/SDI bidirectional Parallel data bit 10 when SER/PAR = 0; serial data input of the SPI interface in serial mode (tie to DGND in hardware serial mode).
56 DB11/SDOB bidirectional Parallel data bit 11 when SER/PAR = 0; serial data output B in serial mode.
57 DB12/SDOA bidirectional Parallel data bit 12 when SER/PAR = 0; serial data output A in serial mode.
58 DB13/OS0 bidirectional Parallel data bit 13 when SER/PAR = 0; oversampling ratio select OS0 in hardware serial mode, latched on full reset.
59 DB14/OS1 bidirectional Parallel data bit 14 when SER/PAR = 0; oversampling ratio select OS1 in hardware serial mode, latched on full reset.
60 DB15/OS2 bidirectional Parallel data bit 15 when SER/PAR = 0; oversampling ratio select OS2 in hardware serial mode, latched on full reset.
61 WR/BURST input Write strobe in software parallel mode; burst mode enable in hardware mode, latched on full reset; connect to DGND in software serial mode.
62 SCLK/RD input Serial clock input in serial mode; parallel read control (active low with CS) in parallel mode.
63 CS input Active-low chip select that frames data transfers; in parallel mode with RD low it enables the DBx output bus.
64 CHSEL0 input Channel selection input bit 0 for hardware-mode channel pair selection (must be stable before CONVST rising edge); tie to DGND in software mode.
65 CHSEL1 input Channel selection input bit 1 for hardware-mode channel pair selection (must be stable before CONVST rising edge); tie to DGND in software mode.
66 CHSEL2 input Channel selection input bit 2 for hardware-mode channel pair selection (must be stable before CONVST rising edge); tie to DGND in software mode.
67 BUSY output Busy output that goes high after a CONVST rising edge and returns low when conversion data is ready to read; read data only after BUSY is low.
68 CONVST input Conversion start input for channel groups A and B; a low-to-high transition initiates conversion of the selected channel pair(s).
69 REGGND power_in Internal analog regulator ground; must connect to the system AGND plane.
70 REGCAP power_out Decoupling pin for the internal analog regulator output, typically 1.87 V; decouple to REGGND with a 10 µF capacitor.
71 VCC power_in Analog supply voltage, 4.7 V to 5.25 V, applied to the front-end amplifiers and ADC core; decouple to AGND with 0.1 µF and 10 µF capacitors in parallel.
72 AGND power_in Analog supply ground pin.
73 V0B input Analog input for channel 0 on ADC B.
74 V0BGND power_in Analog input ground pin for analog input V0B.
75 V1B input Analog input for channel 1 on ADC B.
76 V1BGND power_in Analog input ground pin for analog input V1B.
77 V2B input Analog input for channel 2 on ADC B.
78 V2BGND power_in Analog input ground pin for analog input V2B.
79 V3B input Analog input for channel 3 on ADC B.
80 V3BGND power_in Analog input ground pin for analog input V3B.

Key specifications

Parameter Value
Manufacturer Analog Devices
Package LQFP-80(14x14)
Category Data Acquisition
Pins 80

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential Nonlinearity (DNL) DNL -0.99 0.5 0.99 LSB 3
Integral Nonlinearity (INL) INL -2 1 2 LSB 3
Total Unadjusted Error (TUE) TUE -6 6 LSB ±10 V range 3
Total Unadjusted Error (TUE) TUE -8 8 LSB ±5 V range 3
Total Unadjusted Error (TUE) TUE -10 10 LSB ±2.5 V range 3
Positive Full-Scale Error -32 5 32 LSB External reference, ±10 V range 3
Positive Full-Scale Error -4 4 LSB External reference, ±5 V range 3
Positive Full-Scale Error -2 2 LSB External reference, ±2.5 V range 3
Positive Full-Scale Error -5 5 LSB Internal reference, ±10 V range 3
Positive Full-Scale Error Drift -5 2 5 ppm/°C External reference 4
Positive Full-Scale Error Drift -10 3 10 ppm/°C Internal reference 4
Bipolar Zero Code Error -8 0.8 8 LSB ±10 V range 4
Bipolar Zero Code Error -10 1 10 LSB ±5 V range 4
Bipolar Zero Code Error Drift -20.4 1.3 20.4 μV/°C ±10 V range 4
Negative Full-Scale (NFS) Error -32 4 32 LSB External reference, ±10 V range 4
Negative Full-Scale (NFS) Error -3 3 LSB External reference, ±5 V range 4
Negative Full-Scale (NFS) Error -6 6 LSB External reference, ±2.5 V range 4
Negative Full-Scale Error Drift -5 2 5 ppm/°C External reference 4
Analog Input Current -10.5 10.5 μA ±10 V range, see Figure 34 4
Analog Input Current -6.5 6.5 μA ±5 V range, see Figure 34 4
Analog Input Current -4 4 μA ±2.5 V range, see Figure 34 4
Input Impedance 0.85 1 MΩ See the Analog Input section 4
Reference Input Voltage Range 2.495 2.5 2.505 V See the ADC Transfer Function section 4
Reference Output Voltage REFINOUT 2.495 2.505 V 4
Reference Temperature Coefficient -15 2 15 ppm/°C 4
Input Voltage High (VINH) VINH 2 V VDRIVE = 2.7 V to 3.6 V 4
Input Voltage High (VINH) VINH 1.7 V VDRIVE = 2.3 V to 2.7 V 4
Input Voltage Low (VINL) VINL 0.8 V VDRIVE = 2.7 V to 3.6 V 4
Input Voltage Low (VINL) VINL 0.7 V VDRIVE = 2.3 V to 2.7 V 4
Input Current IIN -1 1 μA 4
Output Voltage Low (VOL) VOL 0.4 V ISINK = 100 μA 5
VCC Supply Voltage VCC 4.75 5.25 V 5
VDRIVE Supply Voltage VDRIVE 2.3 3.6 V 5
Supply Current IVCC, Normal Mode Static IVCC 37 57 mA Normal mode, static 5
Supply Current IVCC, Normal Mode Operational IVCC 42 65 mA Normal mode, fSAMPLE = 1 MSPS 5
Supply Current IDRIVE, Normal Mode Static IDRIVE 0.3 0.75 mA Normal mode, static, digital inputs = 0 V or VDRIVE 5
Supply Current IDRIVE, Normal Mode Operational IDRIVE 7 8 mA Normal mode, fSAMPLE = 1 MSPS, digital inputs = 0 V or VDRIVE 5
Power Dissipation, Normal Mode Static 185 300 mW Normal mode, static 5
Power Dissipation, Normal Mode Operational 230 350 mW Normal mode, fSAMPLE = 1 MSPS 5
Operating Temperature Range TA -40 125 °C 3
VCC to AGND VCC -0.3 7 V 10
Analog Input Voltage to AGND -21 21 V 10
Digital Input Voltage to AGND -0.3 V Max printed as VDRIVE + 0.3 V 10
Digital Output Voltage to AGND -0.3 V Max printed as VDRIVE + 0.3 V 10
Input Current to Any Pin Except Supplies -10 10 mA 10
Operating Temperature Range -40 125 °C 10
Storage Temperature Range -65 150 °C 10
Junction Temperature 150 °C 10
Soldering Reflow Temperature (Pb/Sn) 240 °C 10 sec to 30 sec 10
Soldering Reflow Temperature (Pb-Free) 260 °C 10
Junction-to-Ambient Thermal Resistance θJA 41 °C/W ST-80-21 package, JEDEC 2S2P test board 10
Junction-to-Case Thermal Resistance θJC 7.5 °C/W ST-80-21 package 10
SCLK Setup Time (CS to SCLK falling edge) tSCLK_SETUP 10.5 ns VDRIVE above 3 V 9
SCLK Setup Time (CS to SCLK falling edge) tSCLK_SETUP 13.5 ns VDRIVE above 2.3 V 9
SCLK to CS Rising Edge Hold Time tSCLK_HOLD 10 ns 9
SCLK Low Pulse Width tSCLK_LOW 8 ns 9
SCLK High Pulse Width tSCLK_HIGH 9 ns 9
Data Out Access Time after SCLK Rising Edge tDOUT_SETUP 9 ns VDRIVE above 3 V 9
Data Out Access Time after SCLK Rising Edge tDOUT_SETUP 11 ns VDRIVE above 2.3 V 9
Data In Setup Time before SCLK Falling Edge tDIN_SETUP 10 ns 9
CS Rising Edge to SDOx High Impedance tDOUT_3STATE 10 ns 9

CAD (KiCad official)

  • Symbol: AD7616BSTZ-RL
  • Footprint: Package_QFP:LQFP-80_14x14mm_P0.65mm
  • 3D model: LQFP-80(14x14) (KiCad packages3D, STEP)
  • 3D model files: ad7616bstz-rl-etched.step / ad7616bstz-rl-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ad7616bstz-rl.step / ad7616bstz-rl.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Analog Devices datasheet (50 pp, sha256 1c8b73c9521cdb33, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF